EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 253

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Memory Interfaces Pin Support
Table 8–1. DQS and DQ Bus Mode Pins for Stratix III Devices
Using R
© March 2010 Altera Corporation
×4
×8/×9
×16/×18
×32/×36
Notes to
(1) The QVLD pin is not used in the ALTMEMPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
(3) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(4) Two ×4 DQS/DQ groups are stitched to make a ×8/×9 group, so there are a total of 12 pins in this group.
(5) Four ×4 DQS/DQ groups are stitched to make a ×16/×18 group.
(6) Eight ×4 DQS/DQ groups are stitched to make a ×32/×36 group.
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQS/DQ group in a particular device. Check with the pin table for the accurate number per group. For DDR3,
DDR2, and DDR interfaces, the number of pins is further reduced for interfaces larger than ×8 mode because a DQS pin for each ×8/×9 group
that is used to form the ×16/×18 and ×32/×36 groups is required.
Mode
(4)
Table
(5)
(6)
UP
/R
8–1:
DN
Pins in a DQS/DQ Group Used for Memory Interfaces
DQSn Support
You can also use DQS/DQSn pins in some of the ×4 groups as R
Table
members are being used as RUP and RDN pins for OCT calibration. You may be able to
use the ×8/×9 group that includes this ×4 DQS/DQ group, if either of the following
applies:
■
■
This is because a DQS/DQ ×8/×9 group is comprised of 12 pins, as the groups are
formed by stitching two DQS/DQ groups in ×4 mode with six total pins each
(refer to
eight DQ pins which add up to 10 pins. If you choose your pin assignment carefully,
you can use the two extra pins for RUP and RDN. In a DDR3 SDRAM interface, you
have to use differential DQS, which means that you only have one extra pin. In this
case, pick different pin locations for the RUP and RDN pins (for example, in the bank
that contains the address and control/command pins).
You cannot use RUP and RDN pins shared with DQS/DQ group pins when using ×9
QDR II+/QDR II SRAM devices, as the RUP and RDN pins may have dual purpose
with the CQn pins. In this case, pick different pin locations for RUP and RDN pins to
avoid conflicts with the memory interface pin placement. In this case, you have the
choice of placing the RUP and RDN pins in the data-write group or in the same bank as
the address and control/command pins. There is no restriction when using ×16/×18
or ×32/×36 DQS/DQ groups that include the ×4 groups whose pin members are
being used as RUP and RDN pins, because there are enough extra pins that you can use
as DQS pins.
Yes
Yes
Yes
Yes
You are not using DM pins with your differential DQS pins
You are not using complementary or differential DQS pins
8–1). You cannot use a ×4 DQS/DQ group for memory interfaces if any of its pin
Table
CQn Support
8–1). A typical ×8 memory interface consists of one DQS, one DM, and
Yes
Yes
Yes
No
Parity or DM
(Optional)
No(3)
Yes
Yes
Yes
(Optional)
QVLD
Yes
Yes
Yes
No
(1)
Stratix III Device Handbook, Volume 1
Number of
per Group
Data Pins
16 or 18
32 or 36
Typical
8 or 9
4
UP
/R
DN
pins (listed in
Data Pins per
Number of
Maximum
Group
23
47
11
5
(2)
8–5