EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 250

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

8–2
Figure 8–1. Package Bottom View for Stratix III Devices
Notes to
(1) The number of I/O banks and PLLs available depends on the device density.
(2) There is only one PLL in the center of each side of the device in EP3SL50, EP3SL70, and EP3SE50 devices.
Stratix III Device Handbook, Volume 1
PLL_L4
PLL_L1
PLL_L2
PLL_L3
1A
1B
1C
2C
2B
2A
Figure
DLL1
DLL0
8–1:
8A
3A
Figure 8–1
showing the phase-locked loop (PLL), delay-locked loop (DLL), and I/O banks. The
number of available I/O banks and PLLs depend on the device density.
8B
3B
shows a package bottom view for Stratix III external memory support,
8C
3C
PLL_B1
PLL_T1
Stratix III Device
(Note
1),
PLL_B2
PLL_T2
(2)
Chapter 8: External Memory Interfaces in Stratix III Devices
7C
4C
7B
4B
© March 2010 Altera Corporation
7A
4A
DLL3
DLL2
PLL_R2
PLL_R3
5C
5A
5B
6A
6B
6C
PLL_R4
PLL_R1