EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 216

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

7–12
Figure 7–6. Number of I/Os in Each Bank in EP3SL340 Devices in the 1760-pin FineLine BGA Package
Notes to
(1) All I/O pin counts include dedicated clock inputs pins. The pin count includes all general purpose I/O, dedicated clock pins, and dual-purpose
(2)
Stratix III I/O Structure
Stratix III Device Handbook, Volume 1
configuration pins. Dedicated configuration pins are not included in the pin count.
Figure 7–6
Figure
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
7–6:
The I/O element (IOE) in Stratix III devices contains a bi-directional I/O buffer and
I/O registers to support a complete embedded bi-directional single data rate or DDR
transfer. The IOEs are located in I/O blocks around the periphery of the Stratix III
device. There are up to four IOEs per row I/O block and four IOEs per column I/O
block. The row IOEs drive row, column, or direct link interconnects. The column IOEs
drive column interconnects.
The Stratix III bi-directional IOE also supports the following features:
■
■
■
■
■
■
■
■
Number
of I/Os
Programmable input delay
Programmable output-current strength
Programmable slew rate
Programmable output delay
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination with calibration
50
50
36
50
50
36
Name
Bank
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
EP3SL340
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
Bank 6A
Name
Bank
Chapter 7: Stratix III Device I/O Features
Number
of I/Os
50
36
50
50
36
50
© July 2010 Altera Corporation
(Note
Stratix III I/O Structure
1),
(2)