EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 21

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

List of Tables
List of Tables
Table 1–1: FPGA Family Features for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Table 1–2: Package Options and I/O Pin Counts
Table 1–3: FineLine BGA Package Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Table 1–4: Hybrid FineLine BGA Package Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Table 1–5: Speed Grades for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Table 1–6: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Table 2–1: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Table 3–1: Stratix III Device Routing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Table 3–2: Number of LABs reachable using C4 and R4 interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Table 3–3: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Table 4–1: Summary of TriMatrix Memory Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Table 4–2: TriMatrix Memory Capacity and Distribution in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . 4-3
Table 4–3: Truth Table for ECC Status Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Table 4–4: Stratix III Port Width Configurations for MLABs, M9K Blocks, and M144K Blocks (Single-Port
Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Table 4–5: Stratix III M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) . . . . . . . . . . . 4-13
Table 4–6: Stratix III M144K Block Mixed-Width Configurations (Simple Dual-Port Mode) . . . . . . . . . 4-13
Table 4–7: Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) . . . . . . . . . . . . . . 4-15
Table 4–8: Stratix III M144K Block Mixed-Width Configurations (True Dual-Port Mode) . . . . . . . . . . . 4-16
Table 4–9: Stratix III TriMatrix Memory Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Table 4–10: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Table 5–1: Number of DSP Blocks in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Table 5–2: Stratix III DSP Block Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Table 5–3: Input Register Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5–4: Multiplier Sign Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
Table 5–5: Examples of Shift Operations
Table 5–6: Example of Round-To-Nearest-Even Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
Table 5–7: Comparison of Round-to-Nearest-Integer and Round-to-Nearest-Even . . . . . . . . . . . . . . . . . 5-32
Table 5–8: Examples of Saturation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
Table 5–10: DSP Block Dynamic Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
Table 5–10: Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42
Table 6–1: Clock Resources in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Table 6–2: Clock Input Pin Connectivity to Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8
Table 6–3: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 1) . . . . . . . . . . . . . . . . . 6-9
Table 6–4: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2) . . . . . . . . . . . . . . . . . 6-9
Table 6–5: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 3) . . . . . . . . . . . . . . . . 6-10
Table 6–6: Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 4) . . . . . . . . . . . . . . . . 6-11
Table 6–7: Stratix III Device PLLs and PLL Clock Pin Drivers
Table 6–8: PLL Connectivity to GCLKs on Stratix III Devices
Table 6–9: Regional Clock Outputs From PLLs on Stratix III Devices
Table 6–10: Stratix III Device PLL Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-18
Table 6–11: Stratix III PLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Table 6–12: PLL Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Table 6–13: PLL Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25
Table 6–14: Clock Feedback Mode Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26
Table 6–15: Real-Time PLL Reconfiguration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44
Table 6–16: Top/Bottom PLL Reprogramming Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46
© March 2011 Altera Corporation
(Note 1)
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
(Note 1)
(Note 1)
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12
. . . . . . . . . . . . . . . . . . . . . . . . . 6-11
. . . . . . . . . . . . . . . . . . . . 6-13
Stratix III Device Handbook, Volume 1
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