EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 17

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

List of Figures
Figure 6–23: Phase Relationship Between Clock and Data in Source-Synchronous Mode . . . . . . . . . . . . 6-27
Figure 6–24: Phase Relationship Between Clock and Data LVDS Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 6-27
Figure 6–25: Phase Relationship Between PLL Clocks in No Compensation Mode . . . . . . . . . . . . . . . . . 6-28
Figure 6–26: Phase Relationship Between PLL Clocks in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Figure 6–27: Zero-Delay Buffer Mode in Stratix III PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Figure 6–28: Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . 6-30
Figure 6–29: External Feedback Mode in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-30
Figure 6–30: Phase Relationship Between PLL Clocks in External-Feedback Mode . . . . . . . . . . . . . . . . . 6-31
Figure 6–31: Counter Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-32
Figure 6–32: Automatic Clock Switchover Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
Figure 6–33: Automatic Switchover Upon Loss of Clock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-35
Figure 6–34: Clock Switchover Using the clkswitch (Manual) Control
Figure 6–35: Manual Clock Switchover Circuitry in Stratix III PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
Figure 6–36: VCO Switchover Operating Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
Figure 6–37: Open- and Closed-Loop Response Bode Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-39
Figure 6–38: Loop Filter Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
Figure 6–39: Delay Insertion Using VCO Phase Output and Counter Delay Time . . . . . . . . . . . . . . . . . . 6-42
Figure 6–40: PLL Reconfiguration Scan Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-43
Figure 6–41: PLL Reconfiguration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-45
Figure 6–42: Scan-Chain Order of PLL Components for Top/Bottom PLLs
Figure 6–43: Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix III PLLs . . . . . . . . . . . . 6-47
Figure 6–44: Dynamic Phase Shifting Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-51
Figure 7–1: I/O Banks for Stratix III Devices
Figure 7–2: Number of I/Os in Each Bank in EP3SL50, EP3SL70, and EP3SE50 Devices in 484-Pin FineLine
BGA Package
Figure 7–3: Number of I/Os in Each Bank in the 780-pin FineLine BGA Package
Figure 7–4: Number of I/Os in Each Bank in the 1152-pin FineLine BGA Package
7-10
Figure 7–5: Number of I/Os in Each Bank in EP2SL200, EP3SE260, and EP3SL340 Devices in the 1517-Pin
FineLine BGA Package
Figure 7–6: Number of I/Os in Each Bank in EP3SL340 Devices in the 1760-pin FineLine BGA Package
Figure 7–7: IOE Structure for Stratix III Devices
Figure 7–8: On-Chip Series Termination without Calibration for Stratix III Devices . . . . . . . . . . . . . . . . 7-21
Figure 7–9: On-Chip Series Termination with Calibration for Stratix III Devices . . . . . . . . . . . . . . . . . . . 7-21
Figure 7–10: On-Chip Parallel Termination with Calibration for Stratix III Devices . . . . . . . . . . . . . . . . . 7-24
Figure 7–11: Dynamic Parallel OCT in Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25
Figure 7–12: Differential Input On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26
Figure 7–13: OCT Calibration Block (CB) Location in EP3SL50, EP3SL70, and EP3SE50 Devices
7-27
Figure 7–14: OCT Calibration Block (CB) Location in EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices
Figure 7–15: OCT Calibration Block (CB) Location in EP3SL200, EP3SE260 and EP3SL340
Figure 7–16: Example of Sharing Multiple I/O Banks with One OCT Calibration Block
Figure 7–17: Signals Used for User Mode Calibration
Figure 7–18: OCT User-Mode Signal Timing Waveform for One OCT Block . . . . . . . . . . . . . . . . . . . . . . 7-31
Figure 7–19: OCT User-Mode Signal Timing Waveform for Two OCT Blocks . . . . . . . . . . . . . . . . . . . . . 7-32
Figure 7–20: SSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33
Figure 7–21: HSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34
Figure 7–22: Differential SSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . 7-35
© March 2011 Altera Corporation
(Note
(Note 1)
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12
(Note
1), (2), . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
(Note
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11
(Note
(Note
1), (2), (3), (4), (5), (6), (7), (8),
(Note 1)
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-30
(Note 1)
(Note 1)
Stratix III Device Handbook, Volume 1
. . . . . . . . . . . . . . . . . . . 6-36
(9)
(Note
(Note
. . . . . . . . . . . . . . . 6-47
. . . . . . . . . . . . . . . . 7-6
1), (2), (3),
(Note 1)
1), (2), (3),
(Note 1)
(Note 1)
. . . . 7-29
(4)
. . 7-28
(4)
. 7-9
. . .
xvii
.