EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 125

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 5: DSP Blocks in Stratix III Devices
Operational Mode Descriptions
Double Multiplier
Figure 5–12. Double Mode for Half-DSP Block
© March 2010 Altera Corporation
dataa_0[35..18]
datab_0[35..18]
datab_0[35..18]
dataa_0[35..18]
datab_0[17..0]
dataa_0[17..0]
dataa_0[17..0]
datab_0[17..0]
clock[3..0]
ena[3..0]
aclr[3..0]
The Stratix III DSP block can be configured to efficiently support an unsigned 54 × 54
bit multiplier that is required to compute the mantissa portion of an IEEE double
precision floating point multiplication. A 54 × 54 bit multiplier can be built using basic
18 × 18 multipliers, shifters, and adders. In order to efficiently utilize the Stratix III
DSP block's built in shifters and adders, a special Double mode (partial 54 × 54
multiplier) is available that is a slight modification to the basic 36 × 36 Multiplier
mode. This is shown in
Half-DSP Block
signa
signb
Figure 5–12
+
+
and
Figure
+
5–13.
Stratix III Device Handbook, Volume 1
72
result[ ]
5–19