EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 105

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 4–10. Chapter Revision History
© May 2009 Altera Corporation
May 2009,
version 1.8
February 2009,
version 1.7
November 2008,
Version 1.6
October 2008,
version 1.5
May 2008,
version 1.4
November 2007,
version 1.3
October 2007,
version 1.2
May 2007,
version 1.1
November 2006,
version 1.0
Date and Revision
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■
■
■
■
■
■
■
■
■
■
■
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Updated Table 4–2.
■
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Updated Table 4–2, Table 4–9.
Initial Release.
Table 4–10
Updated
Updated
sections.
Updated Figure 4–2, Figure 4–4, and Figure 4–5.
Removed “Referenced Documents” section.
Updated “Byte-Enable Support”, “Address Clock Enable Support”,
“Asynchronous Clear”, “Single Port RAM”, and “Simple Dual-Port Mode”
sections.
Updated Figure 4–1, Figure 4–5, Figure 4–8, Figure 4–10, and
Figure 4–15.
Added Figure 4–2, Figure 4–6, Figure 4–11, Figure 4–14, and
Figure 4–16.
Updated Table 4–1.
Updated “Asynchronous Clear” and “Clocking Modes” section.
Added “Programming File Compatibility” section.
Updated New Document Format.
Updated “Introduction” section.
Updated “TriMatrix Memory Block Types” section.
Updated “Byte-Enable Support” section.
Updated “Mixed Width Support” section.
Updated “Same-Port Read-During-Write Mode” section.
Updated Figure 4–16, Figure 4–17, and Figure 4–18.
Updated “Mixed-Port Read-During-Write Mode” section.
Updated Table 4–1, Table 4–2, and Table 4–4.
Updated Table 4–1.
Added section “Referenced Documents”.
Added live links for references.
Table
“Read/Write Clock Mode”
shows the revision history for this chapter.
4–1.
Changes Made
and
“Simple Dual-Port Mode”
Stratix III Device Handbook, Volume 1
Summary of Changes
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4–25