EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 34

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

1–24
Table 1–26. DPA Lock Time Specifications for Stratix III Devices
Figure 1–2. DPA Lock Time Specification with DPA PLL Calibration Enabled
Stratix III Device Handbook, Volume 2
Miscellaneous
Notes to
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) These are the number of repetitions for the stated training pattern to achieve 256 data transitions.
(5) Altera recommends PLL re-calibration for the situations below to guarantee DPA locking:
■
■
(6) Slow clock = data rate (Hz)/ Deserialization factor.
Standard
Sparse data transitions. For example: Repeating sequences of ten 1s and ten 0s.
0 PPM frequency difference and/or 0° phase difference between the clock and data.
Table
rx_dpa_locked
1–26:
rx_reset
10101010
01010101
Training
Pattern
Figure 1–2
Transitions
of Training
Repetition
Number of
Pattern
in one
Data
shows the DPA time specification with DPA PLL calibration enabled.
8
8
transitions
256 data
repetitions
Number of
Transition
per 256
Data
(4)
32
32
clock cycles
96 slow
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
PLL calibration
PLL calibration
Condition
with DPA PLL
with DPA PLL
without DPA
without DPA
calibration
calibration
DPA Lock Time
(Note
transitions
256 data
1), (2),
(5)
3×256 data transitions +
3×256 data transitions +
clock cycles
(3)
2×96 slow clock cycles
2×96 slow clock cycles
96 slow
256 data transitions
256 data transitions
(Part 2 of 2)
Min
(6)
(6)
transitions
256 data
© July 2010 Altera Corporation
Switching Characteristics
Typ
—
—
—
—
Max
—
—
—
—