EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 24

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

Table 1–20. PLL Specifications for Stratix III Devices (Part 1 of 3)
f
f
f
t
f
f
t
t
t
t
f
t
t
IN
INPFD
VCO
EINDUTY
OUT
OUT_EXT
OUTDUTY
FCOMP
CONFIGPLL
CONFIGPHASE
SCANCLK
LOCK
DLOCK
Symbol
Input clock frequency
Input frequency to the PFD
PLL VCO operating range
Input clock or external feedback
clock input duty cycle
Output frequency for internal global
or regional clock
Output frequency for dedicated
external clock output
Duty cycle for external clock output
(when set to 50%)
External feedback clock
compensation time
Time required to reconfigure scan
chain
Time required to reconfigure phase
shift
scanclk frequency
Time required to lock from end of
device configuration
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale
counters/delays)
Parameter
Min
600
40
—
—
45
—
—
—
—
—
—
5
5
V
CCL
Typ
= 1.1 V
3.5
C2
—
—
—
—
—
—
50
—
—
—
—
1
1600
Max
800
325
600
800
100
(1)
(2)
(2)
60
55
10
—
—
1
1
Min
600
40
—
—
45
—
—
—
—
—
—
5
5
V
CCL
C3, I3
Typ
3.5
= 1.1 V
—
—
—
—
—
—
50
—
—
—
—
1
1300
Max
717
325
500
717
100
(1)
(2)
(2)
60
55
10
—
—
1
1
Min
600
40
—
—
45
—
—
—
—
—
—
5
5
V
CCL
C4, I4
Typ
= 1.1 V
3.5
—
—
—
—
—
—
50
—
—
—
—
1
1300
Max
717
325
450
717
100
(1)
(2)
(2)
60
55
10
—
—
1
1
Min
600
40
—
—
45
—
—
—
—
—
—
5
5
V
CCL
Typ
3.5
= 1.1 V
—
—
—
—
—
—
50
—
—
—
—
1
1300
Max
717
325
450
717
100
(1)
(2)
(2)
60
55
10
—
—
C4L, I4L
1
1
Min
600
40
—
—
45
—
—
—
—
—
—
5
5
V
CCL
Typ
= 0.9 V
3.5
—
—
—
—
—
—
50
—
—
—
—
1
1300
Max
717
325
375
717
100
(1)
60
(2)
(2)
55
10
—
—
1
1
scanclk
scanclk
cycles
cycles
Unit
MHz
MHz
MHz
MHz
MHz
MHz
ms
ms
ns
%
%