EP2S30F672C3N Altera, EP2S30F672C3N Datasheet - Page 82
EP2S30F672C3N
Manufacturer Part Number
EP2S30F672C3N
Description
IC STRATIX II FPGA 30K 672-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S30F672C3N
Number Of Logic Elements/cells
33880
Number Of Labs/clbs
1694
Total Ram Bits
1369728
Number Of I /o
500
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
No. Of Macrocells
33880
Family Type
Stratix II
No. Of I/o's
500
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
550MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1896
EP2S30F672C3N
EP2S30F672C3N
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S30F672C3N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP2S30F672C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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I/O Structure
Figure 2–49. Signal Path through the I/O Block
2–74
Stratix II Device Handbook, Volume 1
From Logic
To Logic
Array
Array
Row or Column
io_dataouta
io_dataoutb
io_clk[7..0]
io_dataina
io_datainb
io_ce_out
io_ce_in
io_aclr
io_sclr
io_clk
io_oe
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (see the
Figure 2–49
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out.
selection.
Selection
Control
Signal
illustrates the signal paths through the I/O block.
oe
ce_in
ce_out
aclr/apreset
sclr/spreset
clk_in
clk_out
Figure 2–50
To Other
IOEs
“PLLs & Clock Networks”
illustrates the control signal
IOE
Altera Corporation
section).
May 2007
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