EP4CE55F23C7N Altera, EP4CE55F23C7N Datasheet - Page 354
EP4CE55F23C7N
Manufacturer Part Number
EP4CE55F23C7N
Description
IC CYCLONE IV E FPGA 56K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV Er
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CE55F23C7N
Number Of Logic Elements/cells
55856
Number Of Labs/clbs
3491
Total Ram Bits
2340000
Number Of I /o
324
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2683
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4CE55F23C7N
Manufacturer:
ATMEL
Quantity:
4 200
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1–74
Serial Loopback
Figure 1–71. Serial Loopback Path
Note to
(1) Grayed-Out Blocks are Not Active in this mode.
Cyclone IV Device Handbook, Volume 2
Figure 1–71
1
:
Fabric
FPGA
The serial loopback option is available for all functional modes except PIPE mode. In
this mode, the data from the FPGA fabric passes through the transmitter channel and
looped back to the receiver channel, bypassing the receiver buffer, as shown in
Figure
receiver input buffer is not active in this mode. With this option, you can check the
operation of all enabled PCS and PMA functional blocks in the transmitter and
receiver channels.
The transmitter channel sends the data to both the serial output port and the receiver
channel. The differential output voltage on the serial ports is based on the selected
V
different clock domains. You must provide an alignment pattern for the word aligner
to enable the receiver channel to retrieve the byte boundary.
Serial loopback mode can only be dynamically enabled or disabled during user mode
by performing a dynamic channel reconfiguration.
OD
settings. The data is looped back to the receiver CDR and is retimed through
To FPGA fabric
for verification
1–71. The received data is available to the FPGA logic for verification. The
(Note 1)
Transceiver
Tx PCS
Rx PCS
Tx PMA
Rx PMA
Deserializer
Serializer
Chapter 1: Cyclone IV Transceivers Architecture
CDR
© December 2010 Altera Corporation
loopback
Serial
path
Loopback
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