EP2C35F672C8 Altera, EP2C35F672C8 Datasheet - Page 88
![IC CYCLONE II FPGA 33K 672-FBGA](/photos/6/72/67269/ep2c35f672c8_sml.jpg)
EP2C35F672C8
Manufacturer Part Number
EP2C35F672C8
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
475
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1089
EP2C35F672C8ES
EP2C35F672C8ES
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Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
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Power-On Reset Circuitry
4–6
Cyclone II Device Handbook, Volume 1
For Cyclone II devices, wake-up time consists of power-up, POR,
configuration, and initialization. The device must properly go through all
four stages to configure correctly and begin operation. You can calculate
wake-up time using the following equation:
Figure 4–3
Figure 4–3. Cyclone II Wake-Up Time
Note to
(1)
The V
characteristics and the power supply used in your system. The fast-on
devices require a maximum V
POR time of 12 ms.
Configuration time will depend on the configuration mode chosen and
the configuration file size. You can calculate configuration time by
multiplying the number of bits in the configuration file with the period of
the configuration clock. For fast configuration times, you should use
Passive Serial (PS) configuration mode with maximum DCLK frequency
of 100 MHz. In addition, you can use compression to reduce the
configuration file size and speed up the configuration time. The t
or t
1
Wake-Up Time = V
V
CC
Minimum
CD2UMC
V
CC
CC
Figure
ramp must be monotonic.
ramp time and POR time will depend on the device
For more information on the t
to the Configuring Cyclone II Devices chapter in the Cyclone II
Device Handbook.
illustrates the components of wake up time.
parameters will determine the initialization time.
Voltage
V
CC
Time
4–3:
Ramp
CC
Ramp Time + POR Time + Configuration Time + Initialization Time
POR Time
CC
ramp time of 2 ms and have a maximum
Configuration Time
CD2UM
or t
CD2UMC
Altera Corporation
parameters, refer
Initialization
Time
February 2007
CD2UM
Mode
User
Time