EPF6016TI144-3 Altera, EPF6016TI144-3 Datasheet - Page 18
![IC FLEX 6000 FPGA 16K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EPF6016TI144-3
Manufacturer Part Number
EPF6016TI144-3
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet
1.EPF6010ATC100-3N.pdf
(52 pages)
Specifications of EPF6016TI144-3
Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1283
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EPF6016TI144-3
Manufacturer:
ALTERA
Quantity:
1 078
Part Number:
EPF6016TI144-3
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
FLEX 6000 Programmable Logic Device Family Data Sheet
Figure 9. FastTrack Interconnect Architecture
Note:
(1)
18
Adjacent
To/From
LAB
For EPF6010A, EPF6016, and EPF6016A devices, n = 144 channels and m = 20 channels; for EPF6024A devices,
n = 186 channels and m = 30 channels.
10
10
5
Row Interconnect (n Channels) (1)
5
5
2
Local Interconnect (32 Channels)
10
10
10
5
The FastTrack Interconnect consists of column and row interconnect
channels that span the entire device. Each row of LABs is served by a
dedicated row interconnect, which routes signals between LABs in the
same row, and also routes signals from I/O pins to LABs. Additionally,
the local interconnect routes signals between LEs in the same LAB and in
adjacent LABs. The column interconnect routes signals between rows and
routes signals from I/O pins to rows.
LEs 1 through 5 of an LAB drive the local interconnect to the right, while
LEs 6 through 10 drive the local interconnect to the left. The DATA1 and
DATA3 inputs of each LE are driven by the local interconnect to the left;
DATA2 and DATA4 are driven by the local interconnect to the right. The
local interconnect also routes signals from LEs to I/O pins.
an overview of the FLEX 6000 interconnect architecture. LEs in the first
and last columns have drivers on both sides so that all LEs in the LAB can
drive I/O pins via the local interconnect.
5
22
2
5
through
through
LE 10
LE 1
LE 6
LE 5
5
5
10
10
10
10
5
20
5
5
Column Interconnect (m Channels) (1)
2
22
5
10
10
10
5
2
5
through
through
LE 10
LE 1
LE 6
LE 5
5
5
10
10
10
10
5
20
Altera Corporation
Figure 9
10
10
5
shows
To/From
Adjacent
LAB