EP2C8F256I8 Altera, EP2C8F256I8 Datasheet - Page 165
![IC CYCLONE II FPGA 8K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP2C8F256I8
Manufacturer Part Number
EP2C8F256I8
Description
IC CYCLONE II FPGA 8K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8F256I8
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
182
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2150
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8F256I8
Manufacturer:
ALTERA
Quantity:
748
Part Number:
EP2C8F256I8
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP2C8F256I8N
Manufacturer:
ALTBRA
Quantity:
5
Company:
Part Number:
EP2C8F256I8N
Manufacturer:
ALTERA41
Quantity:
106
Part Number:
EP2C8F256I8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
February 2008
February 2007
v3.1
December 2005
v2.2
November 2005
v2.1
July 2005
v2.0
November 2004
v1.1
June 2004
v1.0
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Updated PLL Timing Specifications
Updated technical content throughout.
Updated technical content throughout.
Updated the
Updated
Added document to the Cyclone II Device Handbook.
Added document revision history.
Added V
Table
Updated
Updated the maximum V
“A” devices in
Updated R
Changed V
Updated LVPECL clock inputs in
Table
Updated
Updated C
Table
Updated
Updated
Added
derating factors.
Corrected calculation of the period based on a
640 Mbps data rate as 1562.5 ps in
Table
Updated
Updated V
Table
Updated chapter with extended temperature
information.
Table
5–1.
5–8.
5–13.
5–50.
5–54.
Table 5–46
CCA
Note (1)
Note (1)
“Timing Specifications”
Table
“PLL Timing Specifications”
“Differential I/O Standards”
CO
CONF
V R E F
I
5–54.
to I
minimum and maximum limitations in
range of 300–500 MHz in
Table
5–45.
i
information in
in
capacitance description in
in
to
Table
with information on toggle rate
Table
Table
5–2.
CC
5–3.
5–2.
5–12.
rise time for Cyclone II
Table
section.
Note (6)
5–3.
Note (2)
section.
section.
Note (3)
DC Characteristics and Timing Specifications
to
to
to
Cyclone II Device Handbook, Volume 1
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