EP2C8Q208C7N Altera, EP2C8Q208C7N Datasheet - Page 159
![IC CYCLONE II FPGA 8K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C8Q208C7N
Manufacturer Part Number
EP2C8Q208C7N
Description
IC CYCLONE II FPGA 8K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C8Q208C7N
Number Of Logic Elements/cells
8256
Number Of Labs/clbs
516
Total Ram Bits
165888
Number Of I /o
138
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
8256
# I/os (max)
138
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
8256
Ram Bits
165888
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1672
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA
Quantity:
8
Part Number:
EP2C8Q208C7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 5–10. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
Altera Corporation
February 2008
clk
INPUT
VCC
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–55
derivation for different I/O standards on Cyclone II devices. Examples
are also provided that show how to calculate DCD as a percentage.
LVCMOS
LVTTL
2.5-V
1.8-V
1.5-V
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
HSTL-15 Class I
HSTL-18 Class I
Table 5–55. Maximum DCD for Single Data Outputs (SDR) on Row I/O
Pins
Row I/O Output Standard
Notes
through
(1),
GND
V
CC
(2)
DFF
DFF
5–58
(Part 1 of 2)
D
D
CLRN
CLRN
PRN
PRN
give the maximum DCD in absolution
Q
Q
DC Characteristics and Timing Specifications
145
165
195
120
115
130
Cyclone II Device Handbook, Volume 1
C6
60
65
90
85
1
0
230
255
120
115
130
165
145
155
C7
90
75
230
255
135
175
135
165
205
155
output
C8
90
75
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
5–69