EPF6016TC144-3 Altera, EPF6016TC144-3 Datasheet - Page 23

IC FLEX 6000 FPGA 16K 144-TQFP

EPF6016TC144-3

Manufacturer Part Number
EPF6016TC144-3
Description
IC FLEX 6000 FPGA 16K 144-TQFP
Manufacturer
Altera
Series
FLEX 6000r
Datasheet

Specifications of EPF6016TC144-3

Number Of Logic Elements/cells
1320
Number Of Labs/clbs
132
Number Of I /o
117
Number Of Gates
16000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
544-1282

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Altera Corporation
I/O Elements
An IOE contains a bidirectional I/O buffer and a tri-state buffer. IOEs can
be used as input, output, or bidirectional pins. An IOE receives its data
signals from the adjacent local interconnect, which can be driven by a row
or column interconnect (allowing any LE in the device to drive the IOE) or
by an adjacent LE (allowing fast clock-to-output delays). A FastFLEX
I/O pin is a row or column output pin that receives its data signals from
the adjacent local interconnect driven by an adjacent LE. The IOE receives
its output enable signal through the same path, allowing individual
output enables for every pin and permitting emulation of open-drain
buffers. The Altera Compiler uses programmable inversion to invert the
data or output enable signals automatically where appropriate. Open-
drain emulation is provided by driving the data input low and toggling
the OE of each IOE. This emulation is possible because there is one OE per
pin.
A chip-wide output enable feature allows the designer to disable all pins
of the device by asserting one pin (DEV_OE). This feature is useful during
board debugging or testing.
Figure 12
Figure 12. IOE Block Diagram
shows the IOE block diagram.
Chip-Wide Output Enable
From LAB Local Interconnect
From LAB Local Interconnect
To Row or Column Interconnect
FLEX 6000 Programmable Logic Device Family Data Sheet
Delay
Slew-Rate
Control
TM
23

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