EP2C8F256C8N Altera, EP2C8F256C8N Datasheet - Page 39

• Manufacturer Part Number: EP2C8F256C8N
• Description: IC CYCLONE II FPGA 8K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C8F256C8N

• Number Of Logic Elements/cells: 8256
• Number Of Labs/clbs: 516
• Total Ram Bits: 165888
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 8256
• # I/os (max): 182
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 8256
• Ram Bits: 165888
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1653

Figure 2–16. Cyclone II PLL
Notes to
(1)
(2)
Embedded
Memory
Altera Corporation
February 2007
CLK0 (1)
CLK2 (1)
CLK1
CLK3
This input can be single-ended or differential. If you are using a differential I/O standard, then two CLK pins are
used. LVDS input is supported via the secondary function of the dedicated CLK pins. For example, the CLK0 pin’s
secondary function is LVDSCLK1p and the CLK1 pin’s secondary function is LVDSCLK1n. If a differential I/O
standard is assigned to the PLL clock input pin, the corresponding CLK(n) pin is also completely used. The
Figure 2–16
This counter output is shared between a dedicated external clock output I/O and the global clock network.
Figure
2–16:
shows the possible clock input connections (CLK0/CLK1) to PLL1.
inclk0
inclk1
f
Manual Clock
Select Signal
Switchover
f
IN
Figure 2–16
For more information on Cyclone II PLLs, see the PLLs in the Cyclone II
Devices chapter in Volume 1 of the Cyclone II Device Handbook.
The Cyclone II embedded memory consists of columns of M4K memory
blocks. The M4K memory blocks include input registers that synchronize
writes and output registers to pipeline designs and improve system
performance. The output registers can be bypassed, but input registers
cannot.
÷n
f
Input Clock
REF
f
Reference
FB
Note (1)
= f
IN
/n
PFD
shows a block diagram of the Cyclone II PLL.
down
up
Charge
Pump
Lock Detect
& Filter
÷m
Loop
Filter
Cyclone II Device Handbook, Volume 1
VCO
f
VCO
(3)
÷k
VCO Phase Selection
Selectable at Each
PLL Output Port
8
8
8
Cyclone II Architecture
Post-Scale
Counters
÷c0
÷c1
÷c2
(2)
Global
Clock
Global
Clock
Global
Clock
PLL<#>_OUT
To I/O or
general routing
2–27