EP2C8F256C8N Altera, EP2C8F256C8N Datasheet - Page 153

• Manufacturer Part Number: EP2C8F256C8N
• Description: IC CYCLONE II FPGA 8K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C8F256C8N

• Number Of Logic Elements/cells: 8256
• Number Of Labs/clbs: 516
• Total Ram Bits: 165888
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 8256
• # I/os (max): 182
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 8256
• Ram Bits: 165888
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1653

Altera Corporation
February 2008
Notes to
(1)
(2)
(3)
(4)
(5)
f
(input clock
frequency)
HSIODR
SW
Input jitter
tolerance
t
H S C L K
L O C K
Table 5–51. LVDS Receiver Timing Specification
Symbol
For extended temperature devices, the maximum input clock frequency for x10 through x2 modes is 275 MHz.
For extended temperature devices, the maximum data rate for x10 through x2 modes is 550 Mbps.
For extended temperature devices, the maximum input clock frequency for x1 mode is 340 MHz.
For extended temperature devices, the maximum data rate for x1 mode is 340 Mbps.
For extended temperature devices, the maximum lock time is 500 us.
Table
Conditions
5–51:
×10
×10
×8
×7
×4
×2
×1
×8
×7
×4
×2
×1
—
—
—
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
External Memory Interface Specifications
Table 5–52
Note to
(1)
–6 Speed Grade
Table 5–52. DQS Bus Clock Skew Adder Specifications
Typ
This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×9 DQ group is 155 ps or ±77.5 ps.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Table
Mode
×18
shows the DQS bus clock skew adder specifications.
×9
402.5
402.5
402.5
402.5
402.5
402.5
402.5
Max
805
805
805
805
805
300
500
100
5–52:
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
–7 Speed Grade
DQS Clock Skew Adder
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC Characteristics and Timing Specifications
402.5
402.5
155
190
Max
320
320
320
320
320
640
640
640
640
640
400
500
100
Cyclone II Device Handbook, Volume 1
Min
100
10
10
10
10
10
10
80
70
40
20
10
—
—
—
–8 Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
402.5
402.5
320
320
320
320
320
640
640
640
640
640
100
Max
400
550
Unit
ps
ps
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(5)
(3)
(4)
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps
ps
ps
5–63