EP1K30FC256-3N Altera, EP1K30FC256-3N Datasheet - Page 59

• Manufacturer Part Number: EP1K30FC256-3N
• Description: IC ACEX 1K FPGA 30K 256-FBGA
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K30FC256-3N

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 216
• Total Ram Bits: 24576
• Number Of I /o: 171
• Number Of Gates: 119000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1832; EP1K30FC256-3N

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
t
t
t
t
t
t
t
t
t
t
t
t
Table 27. External Reference Timing Parameters
DRR
Table 28. External Timing Parameters
INSU
INH
OUTCO
PCISU
PCIH
PCICO
Table 29. External Bidirectional Timing Parameters
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Symbol
Symbol
Symbol
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
Contact Altera Applications for test circuit specifications and test conditions.
These timing parameters are sample-tested only.
This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
Tables 27
and their symbols.
through
Parameter
Parameter
Parameter
29
ACEX 1K Programmable Logic Device Family Data Sheet
describe the ACEX 1K external timing parameters
Note (1)
Note (3)
(2)
(3)
(3)
(3)
(3),
(3),
(3),
CI = 35 pF
CI = 35 pF
CI = 35 pF
Conditions
Conditions
Conditions
(4)
(4)
(4)
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