EP1K30FC256-3N Altera, EP1K30FC256-3N Datasheet - Page 39

• Manufacturer Part Number: EP1K30FC256-3N
• Description: IC ACEX 1K FPGA 30K 256-FBGA
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K30FC256-3N

• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 216
• Total Ram Bits: 24576
• Number Of I /o: 171
• Number Of Gates: 119000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-1832; EP1K30FC256-3N

Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
I/O
Configuration
t
t
t
f
f
f
t
t
t
t
R
F
INDUTY
CLK1
CLK2
CLKDEV
INCLKSTB
LOCK
JITTER
OUTDUTY
Table 12. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
To implement the ClockLock and ClockBoost circuitry with the Altera software, designers must specify the input
frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
f
operation. Simulation does not reflect this parameter.
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t
The t
t
CLKDEV
INCLKSTB
JITTER
Input rise time
Input fall time
Input duty cycle
Input clock frequency (ClockBoost clock
multiplication factor equals 1)
Input clock frequency (ClockBoost clock
multiplication factor equals 2)
Input deviation from user specification in
the software
Input clock stability (measured between
adjacent clocks)
Time required for ClockLock or ClockBoost
to acquire lock
Jitter on ClockLock or ClockBoost-
generated clock
Duty cycle for ClockLock or ClockBoost-
generated clock
parameter specifies how much the incoming clock can differ from the specified frequency during device
is lower than 50 ps.
specification is measured under long-term observation. The maximum value for t
(1)
(3)
Parameter
(4)
This section discusses the PCI pull-up clamping diode option, slew-rate
control, open-drain output option, and MultiVolt I/O interface for
ACEX 1K devices. The PCI pull-up clamping diode, slew-rate control, and
open-drain output options are controlled pin-by-pin via Altera software
logic options. The MultiVolt I/O interface is controlled by connecting
V
Altera software via the Global Project Device Options dialog box (Assign
menu).
LOCK
CCIO
value is less than the time required for configuration.
to a different voltage than V
ACEX 1K Programmable Logic Device Family Data Sheet
t
t
INCLKSTB
INCLKSTB
Condition
< 100
< 50
CCINT
. Its effect can be simulated in the
Min
40
25
16
40
Typ
50
JITTER
250
200
25,000
Max
100
60
80
40
10
60
is 200 ps if
5
5
(4)
(4)
PPM
MHz
MHz
Unit
ns
ns
ps
ps
ps
%
%
s
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