EP1K30FC256-3N Altera, EP1K30FC256-3N Datasheet - Page 33

IC ACEX 1K FPGA 30K 256-FBGA

EP1K30FC256-3N

Manufacturer Part Number
EP1K30FC256-3N
Description
IC ACEX 1K FPGA 30K 256-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K30FC256-3N

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
171
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1832
EP1K30FC256-3N

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Figure 16. ACEX 1K Row-to-IOE Connections
Note:
(1)
The values for m and n are shown in
Row FastTrack
Interconnect
n
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see
Table 8
EP1K10
EP1K30
EP1K50
EP1K100
Table 8. ACEX 1K Row-to-IOE Interconnect Resources
Device
lists the ACEX 1K row-to-IOE interconnect resources.
Table
Each IOE can drive two
row channels.
n
n
m
m
8.
Note (1)
ACEX 1K Programmable Logic Device Family Data Sheet
Figure
Channels per Row (n)
m-to-1 multiplexer.
Each IOE is driven by an
16).
144
216
216
312
IOE8
IOE1
Row Channels per Pin (m)
18
27
27
39
33
13

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