EP1K30FC256-3N Altera, EP1K30FC256-3N Datasheet - Page 13

IC ACEX 1K FPGA 30K 256-FBGA

EP1K30FC256-3N

Manufacturer Part Number
EP1K30FC256-3N
Description
IC ACEX 1K FPGA 30K 256-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K30FC256-3N

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
171
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1832
EP1K30FC256-3N

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ACEX 1K Programmable Logic Device Family Data Sheet
If necessary, all EABs in a device can be cascaded to form a single RAM
block. EABs can be cascaded to form RAM blocks of up to 2,048 words
without impacting timing. Altera software automatically combines EABs
to meet a designer’s RAM specifications.
EABs provide flexible options for driving and controlling clock signals.
Different clocks and clock enables can be used for reading and writing to
the EAB. Registers can be independently inserted on the data input, EAB
output, write address, write enable signals, read address, and read enable
signals. The global signals and the EAB local interconnect can drive
write-enable, read-enable, and clock-enable signals. The global signals,
dedicated clock pins, and EAB local interconnect can drive the EAB clock
signals. Because the LEs drive the EAB local interconnect, the LEs can
control write-enable, read-enable, clear, clock, and clock-enable signals.
An EAB is fed by a row interconnect and can drive out to row and column
interconnects. Each EAB output can drive up to two row channels and up
to two column channels; the unused row channel can be driven by other
LEs. This feature increases the routing resources available for EAB
outputs (see
Figures 2
and 4). The column interconnect, which is adjacent
13
to the EAB, has twice as many channels as other columns in the device.
Logic Array Block
An LAB consists of eight LEs, their associated carry and cascade chains,
LAB control signals, and the LAB local interconnect. The LAB provides
the coarse-grained structure to the ACEX 1K architecture, facilitating
efficient routing with optimum device utilization and high performance.
Figure 7
shows the ACEX 1K LAB.
Altera Corporation
13

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