EP1K30QC208-3N Altera, EP1K30QC208-3N Datasheet - Page 43

IC ACEX 1K FPGA 30K 208-PQFP

EP1K30QC208-3N

Manufacturer Part Number
EP1K30QC208-3N
Description
IC ACEX 1K FPGA 30K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K30QC208-3N

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
147
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
ACEX™ 1K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
147
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
1728
Ram Bits
24576
Device System Gates
119000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1836
EP1K30QC208-3N

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Notes to tables:
(1)
(2)
Table 16. 32-Bit IDCODE for ACEX 1K Devices
The most significant bit (MSB) is on the left.
The least significant bit (LSB) for all JTAG IDCODEs is 1.
EP1K10
EP1K30
EP1K50
EP1K100
Device
f
Version
(4 Bits)
0001
0001
0001
0010
ACEX 1K devices include weak pull-up resistors on the JTAG pins.
For more information, see the following documents:
Figure 20
Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in
Altera Devices)
ByteBlasterMV Parallel Port Download Cable Data Sheet
BitBlaster Serial Download Cable Data Sheet
Jam Programming & Test Language Specification
shows the timing requirements for the JTAG signals.
Part Number (16 Bits)
0001 0000 0001 0000
0001 0000 0011 0000
0001 0000 0101 0000
0000 0001 0000 0000
ACEX 1K Programmable Logic Device Family Data Sheet
Note (1)
IDCODE (32 Bits)
Identity (11 Bits)
Manufacturer’s
00001101110
00001101110
00001101110
00001101110
1 (1 Bit)
1
1
1
1
(2)
43
13

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