EP1K30QC208-3N Altera, EP1K30QC208-3N Datasheet - Page 33

IC ACEX 1K FPGA 30K 208-PQFP

EP1K30QC208-3N

Manufacturer Part Number
EP1K30QC208-3N
Description
IC ACEX 1K FPGA 30K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K30QC208-3N

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
147
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
ACEX™ 1K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
147
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
1728
Ram Bits
24576
Device System Gates
119000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1836
EP1K30QC208-3N

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Figure 16. ACEX 1K Row-to-IOE Connections
Note:
(1)
The values for m and n are shown in
Row FastTrack
Interconnect
n
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel (see
Table 8
EP1K10
EP1K30
EP1K50
EP1K100
Table 8. ACEX 1K Row-to-IOE Interconnect Resources
Device
lists the ACEX 1K row-to-IOE interconnect resources.
Table
Each IOE can drive two
row channels.
n
n
m
m
8.
Note (1)
ACEX 1K Programmable Logic Device Family Data Sheet
Figure
Channels per Row (n)
m-to-1 multiplexer.
Each IOE is driven by an
16).
144
216
216
312
IOE8
IOE1
Row Channels per Pin (m)
18
27
27
39
33
13

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