EP2C5Q208C7 Altera, EP2C5Q208C7 Datasheet - Page 15

IC CYCLONE II FPGA 5K 208-PQFP

EP2C5Q208C7

Manufacturer Part Number
EP2C5Q208C7
Description
IC CYCLONE II FPGA 5K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5Q208C7

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
142
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1447

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Figure 2–2. Cyclone II LE
Altera Corporation
February 2007
(DEV_CLRn)
labclkena1
labclkena2
Chip-Wide
labclk1
labclk2
labclr1
labclr2
Reset
data1
data2
data3
data4
Asynchronous
Clock Enable
Clear Logic
Clock &
Select
LAB Carry-In
Look-Up
Figure 2–2
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. Each register has data, clock, clock enable, and clear inputs.
Signals that use the global clock network, general-purpose I/O pins, or
any internal logic can drive the register’s clock and clear control signals.
Either general-purpose I/O pins or internal logic can drive the clock
enable. For combinational functions, the LUT output bypasses the
register and drives directly to the LE outputs.
Each LE has three outputs that drive the local, row, and column routing
resources. The LUT or register output can drive these three outputs
independently. Two LE outputs drive column or row and direct link
routing connections and one drives local interconnect resources, allowing
the LUT to drive one output while the register drives another output. This
feature, register packing, improves device utilization because the device
can use the register and the LUT for unrelated functions. When using
register packing, the LAB-wide synchronous load control signal is not
available. See
Table
(LUT)
Chain
Carry
shows a Cyclone II LE.
Register Chain
Routing From
Previous LE
“LAB Control Signals” on page 2–8
LAB Carry-Out
Synchronous
LAB-Wide
Synchronous
Load
Clear Logic
Load and
Synchronous
LAB-Wide
Clear
Cyclone II Device Handbook, Volume 1
Register Bypass
Packed
Register Select
D
ENA
CLRN
Register
Feedback
Q
for more information.
Cyclone II Architecture
Programmable
Register
Row, Column,
And Direct Link
Routing
Row, Column,
And Direct Link
Routing
Local Routing
Register Chain
Output
2–3

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