EP1K30TC144-3 Altera, EP1K30TC144-3 Datasheet - Page 57
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EP1K30TC144-3
Manufacturer Part Number
EP1K30TC144-3
Description
IC ACEX 1K FPGA 30K 144-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K30TC144-3
Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
102
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1067
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1K30TC144-3
Manufacturer:
ALTERA
Quantity:
11
Company:
Part Number:
EP1K30TC144-3
Manufacturer:
ALTERA
Quantity:
18
Part Number:
EP1K30TC144-3
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Company:
Part Number:
EP1K30TC144-3N
Manufacturer:
ALTERA
Quantity:
900
Company:
Part Number:
EP1K30TC144-3N
Manufacturer:
ALTERA
Quantity:
900
Company:
Part Number:
EP1K30TC144-3N
Manufacturer:
ALTERA
Quantity:
341
Part Number:
EP1K30TC144-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
EABAA
EABRCCOMB
EABRCREG
EABWP
EABWCCOMB
EABWCREG
EABDD
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWEH
EABWDSU
EABWDH
EABWASU
EABWAH
EABWO
Table 25. EAB Timing Macroparameters
Symbol
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Notes
Parameter
ACEX 1K Programmable Logic Device Family Data Sheet
(1),
(6)
Conditions
57
13