EP2C5Q208C8 Altera, EP2C5Q208C8 Datasheet - Page 149
![IC CYCLONE II FPGA 5K 208-PQFP](/photos/6/70/67062/544-208-pqfp_sml.jpg)
EP2C5Q208C8
Manufacturer Part Number
EP2C5Q208C8
Description
IC CYCLONE II FPGA 5K 208-PQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C5Q208C8
Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
142
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
142
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1448
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2C5Q208C8N
Manufacturer:
EPCOS
Quantity:
12 000
Company:
Part Number:
EP2C5Q208C8N
Manufacturer:
ALTERA
Quantity:
15
Company:
Part Number:
EP2C5Q208C8N
Manufacturer:
ALTERA74
Quantity:
619
Part Number:
EP2C5Q208C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Figure 5–5. RSDS Transmitter Clock to Data Relationship
Altera Corporation
February 2008
f
(input
clock
frequency)
H S C L K
Table 5–49. Mini-LVDS Transmitter Timing Specification (Part 1 of 2)
Symbol
Conditions
rx_data[11..0]
tx_data[11..0]
At transmitter
×10
Channel-to-Channel
At receiver
×8
×7
×4
×2
×1
Skew (1.68 ns)
Table 5–49
devices at 311 Mbps. Cyclone II devices cannot receive mini-LVDS data
because the devices are intended for applications where they will be
driving display drivers. A maximum mini-LVDS data rate of 311 Mbps is
supported for Cyclone II devices using DDIO registers. Cyclone II
devices support mini-LVDS only in the commercial temperature range.
Min
10
10
10
10
10
10
–6 Speed Grade
Clock (5.88 ns)
Transmitter
Typ
—
—
—
—
—
—
t
SU
Skew
Total
(2 ns)
shows the mini-LVDS transmitter timing budget for Cyclone II
155.5
155.5
155.5
155.5
155.5
Max
311
Transmitter
Valid
Valid
Data
Data
Min
10
10
10
10
10
10
t
–7 Speed Grade
H
(2 ns)
DC Characteristics and Timing Specifications
Typ
—
—
—
—
—
—
Transmitter
Cyclone II Device Handbook, Volume 1
Valid
Valid
Data
Data
155.5
155.5
155.5
155.5
155.5
Max
311
Min
10
10
10
10
10
10
–8 Speed Grade
Typ
—
—
—
—
—
—
155.5
155.5
155.5
155.5
155.5
Max
311
MHz
MHz
MHz
MHz
MHz
MHz
Unit
5–59