EP2C5T144C8 Altera, EP2C5T144C8 Datasheet - Page 56

IC CYCLONE II FPGA 5K 144-TQFP

EP2C5T144C8

Manufacturer Part Number
EP2C5T144C8
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5T144C8

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1450

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5T144C8
Manufacturer:
ALTERA
Quantity:
20
Part Number:
EP2C5T144C8
Manufacturer:
ALTERA
0
Part Number:
EP2C5T144C8N
Manufacturer:
ALTERA
Quantity:
28
Part Number:
EP2C5T144C8N
Manufacturer:
ALTERA73
Quantity:
6 170
Part Number:
EP2C5T144C8N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2C5T144C8N
Manufacturer:
ALTERA
0
Part Number:
EP2C5T144C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2C5T144C8N
0
Part Number:
EP2C5T144C8N@@@@@
Manufacturer:
ALTERA
0
Part Number:
EP2C5T144C8NK
Manufacturer:
ALTERA
0
I/O Structure & Features
2–44
Cyclone II Device Handbook, Volume 1
Programmable delays can increase the register-to-pin delays for output
registers.
devices.
There are two paths in the IOE for an input to reach the logic array. Each
of the two paths can have a different delay. This allows you to adjust
delays from the pin to internal LE registers that reside in two different
areas of the device. You set the two combinational input delays by
selecting different delays for two different paths under the Input delay
from pin to internal cells logic option in the Quartus II software.
However, if the pin uses the input register, one of delays is disregarded
because the IOE only has two paths to internal logic. If the input register
is used, the IOE uses one input path. The other input path is then
available for the combinational path, and only one input delay
assignment is applied.
The IOE registers in each I/O block share the same source for clear or
preset. You can program preset or clear for each individual IOE, but both
features cannot be used simultaneously. You can also program the
registers to power up high or low after configuration is complete. If
programmed to power up low, an asynchronous clear can control the
registers. If programmed to power up high, an asynchronous preset can
control the registers. This feature prevents the inadvertent activation of
another device’s active-low input upon power up. If one register in an
IOE uses a preset or clear signal then all registers in the IOE must use that
same signal if they require preset or clear. Additionally a synchronous
reset signal is available for the IOE registers.
External Memory Interfacing
Cyclone II devices support a broad range of external memory interfaces
such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDRII SRAM
external memories. Cyclone II devices feature dedicated high-speed
interfaces that transfer data between external memory devices at up to
167 MHz/333 Mbps for DDR and DDR2 SDRAM devices and
167 MHz/667 Mbps for QDRII SRAM devices. The programmable DQS
delay chain allows you to fine tune the phase shift for the input clocks or
strobes to properly align clock edges as needed to capture data.
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Table 2–13. Cyclone II Programmable Delay Chain
Programmable Delays
Table 2–13
shows the programmable delays for Cyclone II
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Quartus II Logic Option
Altera Corporation
February 2007

Related parts for EP2C5T144C8