EP2C5T144C8 Altera, EP2C5T144C8 Datasheet - Page 21

• Manufacturer Part Number: EP2C5T144C8
• Description: IC CYCLONE II FPGA 5K 144-TQFP
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5T144C8

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 89
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Other names: 544-1450

Figure 2–7. LAB-Wide Control Signals
Altera Corporation
February 2007
Dedicated
LAB Row
Clocks
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
This gives a maximum of seven control signals at a time. When using the
LAB-wide synchronous load, the clkena of labclk1 is not available.
Additionally, register packing and synchronous load cannot be used
simultaneously.
Each LAB can have up to four non-global control signals. Additional LAB
control signals can be used as long as they are global signals.
Synchronous clear and load signals are useful for implementing counters
and other functions. The synchronous clear and synchronous load signals
are LAB-wide signals that affect all registers in the LAB.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal also uses labclkena1. If the
LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal turns off the
LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack
allows clock and control signal distribution in addition to data.
shows the LAB control signal generation circuit.
LAB-wide signals control the logic for the register’s clear signal. The LE
directly supports an asynchronous clear function. Each LAB supports up
to two asynchronous clear signals (labclr1 and labclr2).
6
labclk1
labclkena1
labclk2
labclkena2
Cyclone II Device Handbook, Volume 1
™
syncload
interconnect’s inherent low skew
labclr1
Cyclone II Architecture
labclr2
Figure 2–7
synclr
2–9