EP1K10TC100-3N Altera, EP1K10TC100-3N Datasheet - Page 57

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3N

Manufacturer Part Number
EP1K10TC100-3N
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3N

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Family Name
ACEX™ 1K
Number Of Usable Gates
10000
Number Of Logic Blocks/elements
576
# I/os (max)
66
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
576
Ram Bits
12288
Device System Gates
56000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1828
EP1K10TC100-3N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K10TC100-3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA
0
Part Number:
EP1K10TC100-3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
t
t
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t
t
t
t
t
t
t
t
t
t
t
t
t
EABAA
EABRCCOMB
EABRCREG
EABWP
EABWCCOMB
EABWCREG
EABDD
EABDATACO
EABDATASU
EABDATAH
EABWESU
EABWEH
EABWDSU
EABWDH
EABWASU
EABWAH
EABWO
Table 25. EAB Timing Macroparameters
Symbol
EAB address access delay
EAB asynchronous read cycle time
EAB synchronous read cycle time
EAB write pulse width
EAB asynchronous write cycle time
EAB synchronous write cycle time
EAB data-in to data-out valid delay
EAB clock-to-output delay when using output registers
EAB data/address setup time before clock when using input register
EAB data/address hold time after clock when using input register
EAB WE setup time before clock when using input register
EAB WE hold time after clock when using input register
EAB data setup time before falling edge of write pulse when not using input
registers
EAB data hold time after falling edge of write pulse when not using input
registers
EAB address setup time before rising edge of write pulse when not using
input registers
EAB address hold time after falling edge of write pulse when not using input
registers
EAB write enable to data output valid delay
Notes
Parameter
ACEX 1K Programmable Logic Device Family Data Sheet
(1),
(6)
Conditions
57
13

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