XC95144XL-10TQG144C Xilinx Inc, XC95144XL-10TQG144C Datasheet - Page 17
![IC CPLD 3.2K 144MCELL 144-TQFP](/photos/6/70/67094/144tqfp_sml.jpg)
XC95144XL-10TQG144C
Manufacturer Part Number
XC95144XL-10TQG144C
Description
IC CPLD 3.2K 144MCELL 144-TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr
Specifications of XC95144XL-10TQG144C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Memory Type
FLASH
Cpld Type
FLASH
No. Of Macrocells
144
No. Of I/o's
117
Propagation Delay
10ns
Global Clock Setup Time
6.5ns
Frequency
100MHz
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1374
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC95144XL-10TQG144C
Manufacturer:
XILINX44
Quantity:
240
Company:
Part Number:
XC95144XL-10TQG144C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC95144XL-10TQG144C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Further Reading
Further information on the XC9500XL CPLD family can be found at:
http://www.xilinx.com/support/documentation/xc9500xl.htm.
This site includes:
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•
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Revision History
The following table shows the revision history for this document.
DS054 (v2.5) May 22, 2009
Product Specification
09/28/98
10/02/98
02/03/99
04/02/99
06/07/99
06/07/99
01/25/02
02/07/03
08/02/04
11/11/04
07/15/05
03/22/06
07/25/06
04/03/07
11/20/08
05/22/09
Pinouts contained in the density-specific data sheets
Package electrical and thermal characteristics in UG112, Device Package User Guide
Termination, logic thresholds, power sequencing, and slew rate information in UG445, CPLD IO User Guide
Timing model in XAPP111, Using the XC9500XL Timing Model
Good design practices in XAPP784, Bulletproof CPLD Design Practices
Package drawings and dimensions at
Date
R
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
Initial Xilinx release.
Figure 1 correction.
Included hot socket reference; revised layout; BGA package change for XC95288XL.
Minor typesetting corrections.
Minor typesetting corrections.
Added CS280 package.
Added DS054 data sheet number. Added 44-pin VQFP package. Updated Device Family
table.
Added "Further Reading" section.
Added Pb-free documentation.
Changes to package designations in Table 2 on page 2.
Move to Product Specification.
Add Warranty Disclaimer.
Added Subthreshold State to Figure 17 and Table 5, page 16.
Added warning on programming temperature range, page 13.
Updated "Further Reading" section.
Updated description of power sequencing for 5V tolerance in "5V Tolerant I/Os" section.
http://www.xilinx.com/support/documentation/package_specifications.htm
www.xilinx.com
XC9500XL High-Performance CPLD Family Data Sheet
Revision
17