SI5326C-C-GMR Silicon Laboratories Inc, SI5326C-C-GMR Datasheet - Page 62

• Manufacturer Part Number: SI5326C-C-GMR
• Manufacturer: Silicon Laboratories Inc

Si5326
62
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
GND PAD
Pin #
29
28
34
35
36
CKOUT1+
CKOUT2+
Pin Name
CKOUT1–
CKOUT2–
CMODE
GND
GND
I/O
O
O
I
Signal Level
LVCMOS
Supply
Multi
Multi
Output Clock 1.
Differential output clock with a frequency range of 2 kHz to 1.4 GHz.
Output signal format is selected by SFOUT1_REG register bits. Out-
put is differential for LVPECL, LVDS, and CML compatible modes.
For CMOS format, both output pins drive identical single-ended
clock outputs.
Output Clock 2.
Differential output clock with a frequency range of 2 kHz to 1.4 GHz.
Output signal format is selected by SFOUT2_REG register bits. Out-
put is differential for LVPECL, LVDS, and CML compatible modes.
For CMOS format, both output pins drive identical single-ended
clock outputs.
Control Mode.
Selects I
0 = I
1 = SPI Control Mode
This pin must not be NC. Tie either high or low.
See the Si53xx Family Reference Manual for details on I
operation.
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
2
C Control Mode
Rev. 1.0
2
C or SPI control mode for the Si5326.
Description
2
C or SPI