AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet - Page 30

• Manufacturer Part Number: AD9779ABSVZ
• Description: IC DAC 16BIT 1.0GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779ABSVZ

• Data Interface: Serial
• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Resolution: 16b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Interpolation Filter
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3.13V
• Single Supply Voltage (max): 3.47V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / Rohs Status: Compliant

AD9776A/AD9778A/AD9779A
Register Name
Sync Control
Register
Address
0x03
0x03
0x03
0x03
0x04
0x04
0x04
0x05
0x05
0x05
0x06
0x06
0x07
0x07
0x07
0x07
Bits
7
6
5:4
3:0
7:4
3:1
0
7:4
3:1
0
7:4
3:0
7
6
5
4:0
Parameter
DATACLK delay mode
Reserved
DATACLK Divide[1:0]
Data Timing Margin[3:0]
DATACLK Delay[3:0]
SYNC_O Divide[2:0]
SYNC_O Delay[4]
SYNC_O Delay[3:0]
SYNC_I Ratio[2:0]
SYNC_I Delay[4]
SYNC_I Delay[3:0]
SYNC_I Timing Margin[3:0]
SYNC_I enable
SYNC_O enable
SYNC_O triggering edge
Clock State[4:0]
Rev. B | Page 30 of 56
Function
1: automatic data timing error detect mode.
Should always be set to 1.
DATACLK output divider value.
00: divide by 1.
01: divide by 2.
10: divide by 4.
11: divide by 1.
Sets the timing margin required to prevent the
data timing error IRQ bit from being asserted.
Sets delay of REFCLK input to DATACLK output (see
Table 29 for details).
The frequency of the SYNC_O signal is equal to
f
000: N = 32.
001: N = 16.
010: N = 8.
011: N = 4.
100: N = 2.
101: N = 1.
110: N = undefined.
111: N = undefined.
The SYNC_O Delay[4:0] value programs the value
of the delay line of the SYNC_O signal. The delay of
SYNC_O is relative to REFCLK. The delay line
resolution is 80 ps per step.
00000: nominal delay.
00001: adds 80 ps delay to SYNC_O.
00010: adds 160 ps delay to SYNC_O.
…
11111: Adds 2480 ps delay to SYNC_O.
This value controls the number of SYNC_I input
pulses required to generate a synchronization
pulse (see Table 30 for details).
The SYNC_I Delay[4:0] value programs the value of
the delay line of the SYNC_I signal. The delay line
resolution is 80 ps per step.
00000: nominal delay.
00001: adds 80 ps delay to SYNC_I.
00010: adds 160 ps delay to SYNC_I.
…
11111: adds 2480 ps delay to SYNC_I.
1: enables the SYNC_I input.
1: SYNC_O changes on REFCLK rising edge.
This value determines the state of the internal
clock generation state machine upon
synchronization.
0: manual data timing error detect mode.
1: enables the SYNC_O output.
0: SYNC_O changes on REFCLK falling edge.
DAC
/N, where N is set as follows:
Default
0
0
00
0000
0000
000
0
0000
000
0
0000
0000
0
0
0
0