AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet - Page 3

• Manufacturer Part Number: AD9779ABSVZ
• Description: IC DAC 16BIT 1.0GSPS 100TQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9779ABSVZ

• Data Interface: Serial
• Design Resources: Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021)
• Number Of Bits: 16
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Resolution (bits): 16bit
• Sampling Rate: 1GSPS
• Input Channel Type: Parallel
• Digital Ic Case Style: QFP
• No. Of Pins: 100
• Operating Temperature Range: -40°C To +85°C
• Number Of Channels: 2
• Resolution: 16b
• Interface Type: Parallel
• Single Supply Voltage (typ): 3.3V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Interpolation Filter
• Power Supply Requirement: Analog and Digital
• Output Type: Current
• Single Supply Voltage (min): 3.13V
• Single Supply Voltage (max): 3.47V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9779A-EBZ - BOARD EVALUATION FOR AD9779A
• Settling Time: -
• Lead Free Status / Rohs Status: Compliant

REVISION HISTORY
9/08—Rev. A to Rev. B
Changed Serial Peripheral Interface (SPI) to 3-Wire Interface
Change to Features Section .............................................................. 1
Change to Applications Section ...................................................... 1
Changes to Integral Nonlinearity (INL) Parameter, Table 1 ....... 5
Changes to DAC Clock Input (REFCLK+, REFCLK−)
Changes to Input Data Parameter, Table 3 ..................................... 7
Changes to Hold Time Parameters, Table 3 ................................... 7
Added 3-Wire Interface Parameter, Table 3................................... 7
Added Reset Parameter, Table 3 ...................................................... 7
Changes to Endnotes, Table 3 .......................................................... 7
Added Exposed Pad Notation to Figure 3, Changes to Table 7 ...... 10
Added Exposed Pad Notation to Figure 4, Changes to Table 8 ...... 12
Added Exposed Pad Notation to Figure 5, Changes to Table 9 ...... 14
Changes to DATACLK Delay Range Section .............................. 25
Changes to Version Register Section ............................................ 25
Changes to Table 10 ........................................................................ 25
Changes to Table 12 ........................................................................ 26
Changes to Table 13 ........................................................................ 28
Changes to Table 14 ........................................................................ 29
Changes to Interpolation Filter Architecture Section ................ 33
Changes to Figure 60 ...................................................................... 34
Changes to Table 19 ........................................................................ 36
Changes to Interpolation Filter Bandwidth Limits Section ....... 37
Changes to Figure 70 ...................................................................... 37
Added Digital Modulation Section ............................................... 37
Added Table 20 and Table 21; Renumbered Sequentially .......... 38
Added Inverse Sinc Filter Section ................................................. 38
Added Figure 71; Renumbered Sequentially ............................... 38
Changes to Clock Multiplication Section .................................... 39
Changes to Figure 72 ...................................................................... 39
Changes to Configuring the PLL Band Select Value Section .... 39
Changes to Configuring the PLL Band Select with Temperature
Changes to Known Temperature Calibration with Memory
Changes to Set-and-Forget Device Option Section .................... 41
Added Table 26 ................................................................................ 41
Changes to Internal Reference Section......................................... 43
Changed Transmit Path Gain and Offset Correction Heading to
Changes to I/Q Channel Gain Matching Section ....................... 44
Throughout ................................................................................... 1
Parameter, Table 2 ........................................................................ 6
Sensing Section ........................................................................... 41
Section ......................................................................................... 41
Gain and Offset Correction ...................................................... 44
Rev. B | Page 3 of 56
Changes to Auxiliary DAC Operation Section ........................... 44
Replaced Figure 79 .......................................................................... 45
Deleted Figure 79; Renumbered Sequentially ............................. 41
Changes to LO Feedthrough Compensation Section ................. 45
Changes to Table 28 ........................................................................ 47
Changes to Optimizing the Data Input Timing Section ............ 48
Change to Synchronization Logic Overview Section ................. 49
Changes to Figure 88 ...................................................................... 49
Changes to Figure 101 .................................................................... 53
Deleted Using the ADL5372 Quadrature Modulator Section and
Deleted Evaluation Board Schematics Section and Figure 105;
Deleted Figure 106 .......................................................................... 53
Deleted Figure 107 .......................................................................... 54
Deleted Figure 108 .......................................................................... 55
Deleted Figure 109 .......................................................................... 56
Deleted Figure 110 .......................................................................... 57
Deleted Figure 111 .......................................................................... 58
Deleted Figure 112 .......................................................................... 59
Updated Outline Dimensions ........................................................ 60
3/08—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Added Note 2 ..................................................................................... 4
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Thermal Resistance Section ........................................ 7
Inserted Table 6 ................................................................................. 8
Changes to Pin 39 Description, Table 7 ......................................... 9
Changes to Pin 39 Description, Table 8 ....................................... 10
Changes to Pin 39 Description, Table 9 ....................................... 12
Changes to Theory of Operation Section .................................... 23
Changes to Table 10 ........................................................................ 23
Changes to Table 13 ........................................................................ 26
Changes to Table 14 ........................................................................ 27
Changes to Interpolation Filter Architecture Section ................ 33
Replaced Sourcing the DAC Sample Clock Section ................... 36
Replaced Transmit Path Gain and Offset Correction Section ........ 40
Replaced Input Data Ports Section ............................................... 42
Replaced Device Synchronization Section .................................. 45
Deleted Figure 112 to Figure 117 .................................................. 58
8/07—Revision 0: Initial Version
Figure 104 .................................................................................... 51
Renumbered Sequentially ......................................................... 52
AD9776A/AD9778A/AD9779A