EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 53

• Manufacturer Part Number: EWIXP420ABBT
• Manufacturer: Intel

Specifications of EWIXP420ABBT

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

General Hardware Design Considerations—Intel
plane processors
Table 15.
December 2007
Document Number: 252817-008US
Reset Timings Table Parameters
T
T
T
T
T
T
Notes:
1.
2.
3.
RELEASE_PWRON_RST_N
RELEASE_RESET_IN_N
PLL_LOCK
EX_ADDR_SETUP
EX_ADDR_HOLD
WARM_RESET
Symbol
T
programmable-logic device is used to drive the EX_ADDR signals, instead of pull-downs, the signals
must be held stable until the PLL_LOCK goes high.
asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks after
the watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
The expansion bus address is captured during RESET_IN_N signal transition from low to high. When a
PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is
RELEASE_PWRON_RST_N
Intel
Minimum time required to hold
PWRON_RESET_N at logic 0 after a stable
power has been applied to the IXP42X
Product Line and IXC100 Plane
Processors.
Minimum time required to hold the
RESET_IN_N at logic 0 state after
PWRON_RST_N has been released to a
logic 1 state. The RESET_IN_N signal
must be held low when the
PWRON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to
drive to logic 1 after RESET_IN_N is
driven to logic 1 state. The boot
sequence does not occur until this period
is complete.
Minimum time for the EX_ADDR signals
to drive the inputs prior to RESET_IN_N
being driven to logic 1 state. This is used
for sampling configuration information.
Minimum/maximum time for the
EX_ADDR signals to drive the inputs prior
to PLL_LOCK being driven to logic 1
state. This is used for sampling
configuration information.
Minimum time required to hold
RESET_IN_N at logic 0 to cause a Warm
Reset in the IXP42X Product Line and
IXC1100 Plane Processors. During this
period, the power supply must not be
disrupted and PWRON_RESET_N must
remain at logic high during the entire
process.
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
is the time required for the internal oscillator to reach stability.
®
IXP42X product line and IXC1100 control
Parameter
§ §
2000
Min.
500
10
50
0
Typ.
Hardware Design Guidelines
Max.
10
20
Units
ns
ns
µs
ns
ns
ns
Note
1
3
2
2
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