EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 40

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EWIXP420ABBT

Manufacturer Part Number
EWIXP420ABBT
Description
Manufacturer
Intel
Datasheet

Specifications of EWIXP420ABBT

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant

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3.8
3.8.1
Table 10.
Intel
Hardware Design Guidelines
40
UTP_OP_CLK
UTP_OP_FCO
UTP_OP_SOC
UTP_OP_DATA[7:0]
UTP_OP_ADDR[4:0]
UTP_OP_FCI
UTP_IP_CLK
Note:
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Signal
For explanations of the
UTOPIA Interface
The IXP421 and IXP425 processors have the UTOPIA-2 coprocessor and provide an
interface between an internal network processing engine and UTOPIA-2 interface, and
the UTOPIA-2 interface is an industry-standard bus for connecting to ATM physical
devices (PHYs).
The UTOPIA-2 coprocessor is configured as a master. The UTOPIA-2 interface supports
up to four external UTOPIA-2 devices and eight logical channels with cell-level or octet-
level handshaking. The network processing engine handles segmentation and
reassembly of ATM cells, CRC checking/generation, and transfer of data to/from
memory. This allows parallel processing of data traffic on the UTOPIA-2 interface, off-
loading processor overhead required by the Intel XScale
The IXP421 and IXP425 processors are compliant with the ATM Forum, UTOPIA Level-2
Specification, Revision 1.0; for optimal design results, it is recommended to follow the
guidelines of the Specification.
Interface Signals
Interface Signals (Sheet 1 of 2)
• The processors’ USB drivers are the CMOS drivers. To achieve matching
impedance, series resistors are included on both USB_DPOS and USB_DNEG
differential driver lines. The value of the series resistor depends upon the variation
of the driver’s impedance.
I/O*
Intel
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®
Type
IXP42X product line and IXC1100 control plane processors—General Hardware Design
UTOPIA Transmit clock input. Also known as UTP_TX_CLK. This signal is used to synchronize
all UTOPIA-transmit outputs to the rising edge of the UTP_OP_CLK.
This signal should be pulled high through a 10-kΩ resistor, if not being used.
UTOPIA flow control output signal. Also known as the TXENB_N signal.
Used to inform the selected PHY that data is being transmitted to the PHY. Placing the PHY’s
address on the UTP_OP_ADDR — and bringing UTP_OP_FCO to logic 1, during the current
clock — followed by the UTP_OP_FCO going to a logic 0, on the next clock cycle, selects which
PHY is active in MPHY mode.
In SPHY configurations, UTP_OP_FCO is used to inform the PHY that the processor are ready
to send data.
Start of Cell. Also known as TX_SOC.
Active high signal is asserted when UTP_OP_DATA contains the first valid byte of a transmitted
cell.
UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to
an ATM UTOPIA-Level-2-compliant PHY.
Transmit PHY address bus. Used by the processor when operating in MPHY mode to poll and
select a single PHY at any given time.
UTOPIA Output data flow control input: Also known as the TXFULL/CLAV signal.
Used to inform the IXP42X product line and IXC1100 control plane processors of the ability of
each polled PHY to receive a complete cell. For cell-level flow control in an MPHY environment,
TxClav is an active high tri-stateable signal from the MPHY to ATM layer. The UTP_OP_FCI,
which is connected to multiple MPHY devices, will see logic high generated by the PHY, one
clock after the given PHY address is asserted — when a full cell can be received by the PHY.
The UTP_OP_FCI will see a logic low generated by the PHY one clock cycle, after the PHY
address is asserted — if a full cell cannot be received by the PHY.
This signal should be pulled high through a 10-kΩ resistor if not being used.
UTOPIA Receive clock input. Also known as UTP_RX_CLK.
This signal is used to synchronize all UTOPIA-received inputs to the rising edge of the
UTP_IP_CLK.
This signal should be pulled high through a 10-kΩ resistor, if not being used.
column abbreviations, see
Table 21 on page
Description
81.
®
Processor.
Document Number: 252817-008US
Considerations
December 2007

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