EWIXP420ABBT Intel, EWIXP420ABBT Datasheet - Page 30

• Manufacturer Part Number: EWIXP420ABBT
• Manufacturer: Intel

Specifications of EWIXP420ABBT

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Table 6.
3.3.2
Intel
Hardware Design Guidelines
30
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
UART Interface Signals (Sheet 2 of 2)
High-Speed UART
The High-Speed UART interface for the IXP42X product line and IXC1100 control plane
processors can be configured to support speeds from 1,200 baud to 921 Kbaud. This
interface supports five, six, seven, or eight data bit transfers, one or two stop bits, as
well as even-, odd-, or no-parity configurations.
Figure 8
transceiver. This RS-232 transceiver has five transmit and three receive signals to
handle all modem control signals.
For Mbaud signals, options are provided for pull up so that 1-Mbps transmission rate is
achieved, or pull down so that 250 Kbps transmission rate can be set. The default
setting is 1 Mbps. To allow full modem control on the fast UART connection, system
designers have to use four GPIO pins to generate the RS-232 signals (DTR, DSR, RI,
and DCD) that are not available on the processor high-speed UART interfaces.
RXDATA1
TXDATA1
RTS0_N
CTS1_N
RTS1_N
Name
Intel
illustrates how the processors’ UART signals are connected to the RS-232
®
IXP42X product line and IXC1100 control plane processors—General Hardware Design
Type*
O
O
O
I
I
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to the UART
interface of the processor that the UART is ready to exchange data. A reset sets
the request to send signal to logic 1.
Loop-mode operation holds this signal in its inactive state (logic 1). High-Speed
UART pins.
UART serial data input.
When not being used in the system, should be pulled high with a 10-kΩ resistor.
UART serial data output. The TXD signal is set to the MARKING (logic 1) state
upon a reset operation. Console UART pins.
UART CLEAR-TO-SEND input to Console UART pins.
When logic 0, this pin indicates that the modem or data set connected to the
UART interface of the processor is ready to exchange data. The CTS_N signal is a
modem status input whose condition can be tested by the processor.
When not being used in the system, should be pulled high with a 10-kΩ resistor.
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to the UART
interface of the processor that the UART is ready to exchange data. A reset sets
the request to send signal to logic 1.
Loop-mode operation holds this signal in its inactive state (logic 1). Console UART
pins.
Description
Document Number: 252817-008US
Considerations
December 2007