GCIXP1250BA 837411 Intel, GCIXP1250BA 837411 Datasheet - Page 143

• Manufacturer Part Number: GCIXP1250BA 837411
• Manufacturer: Intel

Specifications of GCIXP1250BA 837411

• Lead Free Status / Rohs Status: Supplier Unconfirmed

4.4
Datasheet
Figure 80. SDRAM Read-Modify-Write Cycle
Asynchronous Signal Timing Descriptions
RESET_IN_L Must remain asserted for 150 ms after VDD and VDDX are stable to properly reset the
RESET_OUT_LIs asserted for all types of reset (hard, watchdog, and software) and appears on the pin
GPIO[3:0]
TXD, RXD
Notes:
1. Parameters tRWT, tDPL, tDQZ, tRC, tRRD, tRCD, tRASmin, and tRP programmed into register SDRAM_MEMCTL1
2. CAS Latency value (CASL) = 3 programmed in SDRAM_MEMCTL0
SDCLK
RAS_L
CAS_L
MADR
MDAT
WE_L
DQM
IXP1250.
asynchronously to all clocks.
Are read and written under software control. When writing a value to these pins, the pins
transition approximately 20 ns after the write is performed. When reading these pins, the signal
is first synchronized to the internal clock and must be valid for at least 20 ns before it is visible
to a processor read.
Are asynchronous relative to any device outside the IXP1250.
command
Activate
tRCD
tRASmin
command
Read
DQM remains high
during modify
tDQZ
Intel
®
tRWT
command
IXP1250 Network Processor
Write
Precharge
command
tDPL
DQM remains high
until next read or
write command
A8627-01
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