GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 59

• Manufacturer Part Number: GWIXP460BAD
• Manufacturer: Intel

Specifications of GWIXP460BAD

• Core Operating Frequency: 533MHz
• Operating Supply Voltage (typ): 1.3/1.5/2.5/3.3V
• Operating Supply Voltage (max): 1.575/2.7/3.465V
• Operating Supply Voltage (min): 1.235/2.3/3.135V
• Package Type: BGA
• Pin Count: 544
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Package Information
Table 15.
May 2005
59
UTP_OP_CLK /
ETHA_TXCLK
UTP_OP_FCO
UTP_OP_SOC
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
†† For information on selecting the desired interface, see the Intel
Name
see
Table 1 on page
UTOPIA Level 2/MII_A/ SMII[4] Interface (Sheet 1 of 9)
Power
Reset
on
Z
Z
Z
14.
†
Reset
VI
Z
Z
Table 10 on page
†
Software
Enables
Normal
Reset
After
Until
VI
Z
Z
46.
Software
Enables
Normal
After
VO
VO
®
VI
IXP45X and Intel
®
IXP45X and Intel
Type
TRI
TRI
I
†
UTOPIA Mode of Operation:
UTOPIA Transmit clock input. Also known as UTP_TX_CLK. This signal is used to synchronize all
UTOPIA transmit outputs to the rising edge of the UTP_OP_CLK.
MII Mode of Operation:
Externally supplied transmit clock.
SMII Mode of Operation:
Not Used.
When this interface/signal is enabled and is not being used in a system design, the interface/
signal should be pulled high with a 10-KΩ resistor.
UTOPIA flow control output signal. Also known as the TXENB_N signal.
Used to inform the selected PHY that data is being transmitted to the PHY. Placing the PHY’s
address on the UTP_OP_ADDR — and bringing UTP_OP_FCO to logic 1, during the current
clock — followed by the UTP_OP_FCO going to a logic 0, on the next clock cycle, selects which
PHY is active in MPHY mode.
In SPHY configurations, UTP_OP_FCO is used to inform the PHY that the processor is ready to
send data.
This signal must be tied to Vcc with an external 10-KΩ resistor.
Start of Cell. Also known as TX_SOC.
Active high signal is asserted when UTP_OP_DATA contains the first valid byte of a transmitted
cell.
This signal must be tied to Vss with an external 10-KΩ resistor.
®
• 25 MHz for 100 Mbps operation
• 2.5 MHz for 10 Mbps
IXP46X Product Line of Network Processors. For details on feature support listed by processor,
®
IXP46X Product Line of Network Processors Developer’s Manual.
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
Document Number:
306261-002