GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 50

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Package Information
Table 12.
May 2005
50
PCI_AD[31:0]
PCI_CBE_N[3:0]
PCI_PAR
PCI_FRAME_N
NOTE: This table discusses all features supported on the Intel
† For a legend of the Type codes, see
Name
processor, see
PCI Controller (Sheet 1 of 5)
Reset
Power
Table 1 on page
on
Z
Z
Z
Z
Reset
Z
Z
Z
Z
Table 10 on page
14.
Software
Enables
Normal
Reset
After
Until
VB
VB
VB
VB
Software
Enables
Normal
46.
After
VB
VB
VB
VB
®
IXP45X and Intel
Type
I/O
I/O
I/O
I/O
PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI
devices.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Command/Byte Enables is used as a command word during PCI address cycles and as byte
enables for data cycles.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Parity used to check parity across the 32 bits of PCI_AD and the four bits of PCI_CBE_N.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
PCI Cycle Frame used to signify the beginning and duration of a transaction. The signal will be
inactive prior to or during the final data phase of a given transaction.
When this interface/signal is enabled and is not being used in a system design, the interface/signal
should be pulled high with a 10-KΩ resistor. When this interface is disabled via the PCI soft fuse
(refer to Expansion Bus Controller chapter of the Intel
Network Processors Developer’s Manual) and is not being used in a system design, this interface/
signal is not required for any connection.
®
IXP46X Product Line of Network Processors. For details on feature support listed by
Intel
®
IXP45X and Intel
®
Description
IXP46X Product Line of Network Processors Datasheet
®
®
®
®
IXP45X and Intel
IXP45X and Intel
IXP45X and Intel
IXP45X and Intel
Document Number:
®
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®
IXP46X Product Line of
IXP46X Product Line of
IXP46X Product Line of
IXP46X Product Line of
306261-002

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