GWIXP460BAD Intel, GWIXP460BAD Datasheet - Page 22

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GWIXP460BAD

Manufacturer Part Number
GWIXP460BAD
Description
Manufacturer
Intel
Datasheet

Specifications of GWIXP460BAD

Core Operating Frequency
533MHz
Operating Supply Voltage (typ)
1.3/1.5/2.5/3.3V
Operating Supply Voltage (max)
1.575/2.7/3.465V
Operating Supply Voltage (min)
1.235/2.3/3.135V
Package Type
BGA
Pin Count
544
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Not Compliant
Functional Overview
3.1.2.3
3.1.2.4
3.1.3
May 2005
22
Accesses across the APB/AHB bridge allows interfacing to peripherals attached to the APB. The
Expansion bus and PCI controller can be configured to support split transfers.
Arbitration on the South AHB are round-robin. Each transaction can be no longer than an eight-
word burst. This implementation promotes fairness within the system.
Memory Port Interface
The Memory Port Interface (MPI) is a 128-bit bus that provides the Intel XScale core a dedicated
interface to the DDRI SDRAM. The Memory Port Interface operates at 133.32 MHz (which is 4 *
OSC_IN input pin).
The Memory Port Interface stores memory transactions from the Intel XScale core which have not
been processed by the Memory Controller. The Memory Port Interface supports eight core
processor read transactions up to 32 bytes each. That total equals the maximum number of
outstanding transaction the Core Processor Bus Controller can support. (That includes core DCU
[4 - load requests to unique cache lines], IFU [2 - prefetch], IMM [1 - tablewalk], DMM [1 -
tablewalk].)
The Memory Port Interface also supports eight core-processor-posted write transactions up to
16 bytes each.
Arbitration on the Memory Port Interface is not required due to no contention with other masters.
Arbitration will exist in the DDRI memory controller between all of the main internal busses.
APB Bus
The APB Bus is a 66.66-MHz (which is 2* OSC_IN input pin), 32-bit bus that can be mastered by
the AHB/APB bridge only. The targets of the APB bus can be:
The APB interface is also used as an alternate-path interface to the NPEs and is used for NPE code
download and configuration.
No arbitration is required due to a single master implementation.
MII/SMII Interfaces
The IXP45X/IXP46X network processors can be configured to support up to three MII, up to six
SMII/SS-SMII industry-standard, or some combination thereof, media-independent interface (MII)
interfaces. These interfaces are integrated into the IXP45X/IXP46X network processors with
separate media-access controllers and in many cases independent network processing engines. (See
Table 3
USB 1.1 device controller
The internal bus performance monitoring unit (IBPMU)
GPIO
IEEE 1588 Hardware Assist
I
2
C
for allowable combinations.)
Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors Datasheet
UARTs
All NPEs
Interrupt controller
Timers
Serial Peripheral Port Interface
Document Number:
306261-002

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