PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 34

PRIXP425BC 869083

Manufacturer Part Number
PRIXP425BC 869083
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425BC 869083

Core Operating Frequency
400MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
3.1
Table 7.
Intel
Datasheet
34
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Pin Description Tables
This section identifies all the signal pins by symbol name, type and description. Names
should follow the following convention, all capital letters with a trailing “_N” indicate a
signal is asserted when driven to a logic low (digital 0). The description includes the full
name of the pin along with a functional description. This section does not specify the
number of power and ground pins required, but does include the number of different
types of power pins required.
A signal called active high specifies that the interface is active when driven to a logic 1
and inactive when driven to a logic 0.
A signal called active low specifies that the interface is active when driven to a logic 0
and inactive when driven to a logic 1.
The following information attempts to explain how to interpret the tables. There are
five vertical columns:
SDRAM Interface (Sheet 1 of 2)
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_CLKOUT
SDM_BA[1:0]
SDM_RAS_N
SDM_CAS_N
SDM_CS_N[1:0]
SDM_WE_N
• The Power Reset or Sys Reset column indicates signal state for the following
• The Post Reset column indicates signal state for the following condition:
conditions:
— Power Reset is defined as follows:
— Sys Reset is defined as follows:
— Post Reset is defined as follows:
Name
For a legend of the Type codes, see
PWRON_RESET_N = 0 and RESET_IN_N = X
PWRON_RESET_N = 1 and RESET_IN_N = 0
PWRON_RESET_N = 1, RESET_IN_N = 1 and PLL_LOCK = 1
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Z
Z
Z
Reset
Post
0
1
1
0
1
0
1
1
Intel
Type
I/O
O
O
O
O
O
O
O
®
IXP42X product line and IXC1100 control plane processors
Table 5 on page
SDRAM Address: A0-A12 signals are output during the READ/
WRITE commands and ACTIVE commands to select a location
in memory to act upon.
SDRAM Data: Bidirectional data bus used to transfer data to
and from the SDRAM
SDRAM Clock: All SDRAM input signals are sampled on the
rising edge of SDM_CLKOUT. All output signals are driven
with respect to the rising edge of SDM_CLKOUT.
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the
bank the current command is attempting to access.
SDRAM Row Address strobe/select (active low): Along with
SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDRAM Column Address strobe/select (active low): Along
with SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDRAM Chip select (active low): CS# enables the command
decoder in the external SDRAM when logic low and disables
the command decoder in the external SDRAM when logic
high.
SDRAM Write enable (active low): Along with SDM_CAS_N,
SDM_RAS_N, and SDM_CS_N signals determines the current
command to be executed.
33.
Description
Document Number: 252479-006US
August 2006

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