MT47H32M16BN-37E:D Micron Technology Inc, MT47H32M16BN-37E:D Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT47H32M16BN-37E:D
Manufacturer Part Number
MT47H32M16BN-37E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H32M16BN-37ED.pdf
(139 pages)
Specifications of MT47H32M16BN-37E:D
Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
500ps
Maximum Clock Rate
533MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
205mA
Pin Count
84
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H32M16BN-37E:D
Manufacturer:
MICRON
Quantity:
489
Company:
Part Number:
MT47H32M16BN-37E:D
Manufacturer:
MICRON
Quantity:
319
Company:
Part Number:
MT47H32M16BN-37E:D TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 3: FBGA 84-Ball – x16 and 60-Ball – x4, x8 Descriptions
PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
M8, M3, M7,
N2, N8, N3,
N7, P2, P8,
Number
x16 Ball
P3, M2,
P7, R2
L2, L3
J8, K8
K2
–
x4, x8 Ball
H8, H3, H7,
J7, K2, K8,
Number
J2, J8, J3,
K3, H2,
K7, L2,
G2, G3
E8, F8
L8
F2
–
A11, A12,
BA0, BA1
A11, A12
Symbol
A9, A10,
A9, A10,
CK, CK#
A0–A2,
A3–A5,
A6–A8,
A0–A2,
A3–A5,
A6–A8,
A13
CKE
Input
Input
Input
Input
Input
Type
Description
Address inputs: Provide the row address for ACTIVATE com-
mands, and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH).
The address inputs also provide the op-code during a LOAD MODE
command.
Address inputs: Provide the row address for ACTIVATE com-
mands, and the column address and auto precharge bit (A10) for
READ/WRITE commands, to select one location out of the memory
array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH).
The address inputs also provide the op-code during a LOAD MODE
command.
Bank address inputs: BA[1:0] define to which bank an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. BA[2:0]
define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and con-
trol input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQ and DQS/DQS#)
is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specif-
ic circuitry that is enabled/disabled is dependent on the DDR2
SDRAM configuration and operating mode. CKE LOW provides pre-
charge power-down and SELF REFRESH operations (all banks idle),
or ACTIVATE power-down (row active in any bank). CKE is synchro-
nous for power-down entry, power-down exit, output disable, and
for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit.
Input buffers (excluding CK, CK#, CKE, and ODT) are disabled dur-
ing POWER-DOWN. Input buffers (excluding CKE) are disabled dur-
ing SELF REFRESH. CKE is an SSTL_18 input but will detect a
LVCMOS LOW level once Vdd is applied during first power-up. Af-
ter Vref has become stable during the power-on and initialization
sequence, it must be maintained for proper operation of the CKE
receiver. For proper SELF-REFRESH operation, Vref must be main-
tained.
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Ball Assignments and Descriptions
512Mb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.