AD5625BRUZ Analog Devices Inc, AD5625BRUZ Datasheet - Page 25

• Manufacturer Part Number: AD5625BRUZ
• Description: IC DAC NANO 12BIT QUAD 14-TSSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5625BRUZ

• Data Interface: I²C, Serial
• Settling Time: 3µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 14-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 333kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 2.7V To 5.5V
• Supply Current: 1.9mA
• Digital Ic Case Style: TSSOP
• No.: RoHS Compliant
• Number Of Channels: 4
• Resolution: 12b
• Conversion Rate: 333KSPS
• Interface Type: Serial (2-Wire/I2C)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Compliant

HIGH SPEED MODE
Some models offer high speed serial communication with a
clock frequency of 3.4 MHz. See the Ordering Guide for a full
list of models.
High speed mode communication commences after the master
addresses all devices connected to the bus with the Master Code
00001XXX to indicate that a high speed mode transfer is to
begin. No device connected to the bus is permitted to acknowl-
edge the high speed master code; therefore, the code is followed
by a no acknowledge. Next, the master must issue a repeated
start followed by the device address. The selected device then
acknowledges its address. All devices continue to operate in
high speed mode until the master issues a stop condition. When
the stop condition is issued, the devices return to standard/fast
mode. The part also returns to standard/fast mode when CLR is
activated while the part is in high speed mode.
(CONTINUED)
(CONTINUED)
SCL
SDA
SCL
SDA
START BY
MASTER
SDA
SCL
START BY
MASTER
1
0
1
0
DB15 DB14 DB13 DB12
1
0
0
1
SLAVE ADDRESS
0
Figure 61. Placing the AD56x5RBRUZ-2/AD56x5RBRUZ-2REEL7 in High Speed Mode
FRAME 1
A3
MASTER CODE
FAST MODE
0
HS-MODE
MOST SIGNIFICANT
A2
1
DATA BYTE
FRAME 3
DB11 DB10
A1
X
Figure 60. I
A0
X
R/W
DB9
2
ACK. BY
C Read Operation (14-Lead Package)
AD56x5
X
Rev. B | Page 25 of 36
NO ACK.
9
DB8
9
AD5625R/AD5645R/AD5665R, AD5625/AD5665
MASTER
ACK. BY
1
9
DB23
SR
DB22 DB21 DB20 DB19 DB18 DB17
1
DB7
INPUT SHIFT REGISTER
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock
input, SCL. The timing diagram for this operation is shown in
Figure 3. The eight MSBs make up the command byte. DB23
is reserved and should always be set to 0 when writing to the
device. DB22 (S) is used to select multiple byte operation.
The next three bits are the command bits (C2, C1, and C0)
that control the mode of operation of the device. See Table 10
for details. The last three bits of the first byte are the address bits
(A2, A1, and A0). See Table 11 for details. The rest of the bits
are the 16-/14-/12-bit data-word. The data-word comprises the
16-/14-/12-bit input code followed by two or four don’t care bits
for the AD5645R and the AD5625R/AD5625, respectively (see
Figure 64 through Figure 66).
MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD56x5R/AD56x5.
A 2-byte operation is useful for applications that require fast
DAC updating and do not need to change the command byte.
The S bit (DB22) in the command register can be set to 1 for
2-byte mode of operation (see Figure 63). For standard 3-byte
and 4-byte operation, the S bit (DB22) in the command byte
should be set to 0 (see Figure 62).
1
0
DB6
0
COMMAND BYTE
DB5
FRAME 2
HIGH-SPEED MODE
1
LEAST SIGNIFICANT
ADDRESS BYTE
DB4
SERIAL BUS
DATA BYTE
A3
FRAME 4
DB3
A2
DB2
A1
DB16
DB1
A0
ACK. BY
MASTER
9
DB0
R/W
NO ACK.
9
9
ACK. BY
AD56x5
STOP BY
MASTER