MCP4012T-503E/CH Microchip Technology, MCP4012T-503E/CH Datasheet - Page 43
![IC DGTL POT 50K 1CH RHEO SOT23-6](/photos/6/59/65928/sot-23-6_pkg_sml.jpg)
MCP4012T-503E/CH
Manufacturer Part Number
MCP4012T-503E/CH
Description
IC DGTL POT 50K 1CH RHEO SOT23-6
Manufacturer
Microchip Technology
Datasheet
1.MCP4013T-103ECH.pdf
(60 pages)
Specifications of MCP4012T-503E/CH
Taps
64
Resistance (ohms)
50K
Number Of Circuits
1
Temperature Coefficient
150 ppm/°C Typical
Memory Type
Volatile
Interface
Up/Down
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
SOT-23-6
Resistance In Ohms
50K
End To End Resistance
50kohm
No. Of Steps
64
Resistance Tolerance
± 20%
Supply Voltage Range
1.8V To 5.5V
Control Interface
Increment Decrement
No. Of Pots
Single
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
MCP4012T-503E/CHTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP4012T-503E/CH
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
7.0
In the design of a system with the MCP401X devices,
the following considerations should be taken into
account:
• The Power Supply
• The Layout
7.1
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity.
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (V
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
FIGURE 7-1:
Connections.
© 2006 Microchip Technology Inc.
SS
should reside on the analog plane.
W
A
B
DESIGN CONSIDERATIONS
Power Supply Considerations
0.1 µF
V
V
DD
SS
Typical Microcontroller
Figure 7-1
0.1 µF
U/D
CS
V
V
illustrates an
DD
SS
DD
DD
) as
and
7.2
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4011/2/3/4’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
Layout Considerations
MCP4011/2/3/4
DS21978C-page 43