KAD5512P-21Q72 Intersil, KAD5512P-21Q72 Datasheet - Page 35
![IC ADC 12BIT 210MSPS SGL 72-QFN](/photos/28/17/281743/72-vfqfn_l72d_sml.jpg)
KAD5512P-21Q72
Manufacturer Part Number
KAD5512P-21Q72
Description
IC ADC 12BIT 210MSPS SGL 72-QFN
Manufacturer
Intersil
Series
FemtoCharge™r
Datasheet
1.KAD5512P-25Q72.pdf
(36 pages)
Specifications of KAD5512P-21Q72
Number Of Bits
12
Sampling Rate (per Second)
210M
Data Interface
Serial, SPI™
Number Of Converters
1
Power Dissipation (max)
271mW
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
72-VFQFN Exposed Pad
For Use With
KDC5512EVAL - DAUGHTER CARD FOR KAD5512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.80 Sq
Package Outline Drawing
L48.7x7E
48 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 2/09
INDEX AREA
(4X)
5.60 Sq
PIN 1
6
0.15
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
35
7.00
A
7.00
B
48X 0.60
44X 0.50
48X 0.25
KAD5512P
NOTES:
1.
2.
3.
4.
5.
6.
7.
Exp. DAP
5.60 Sq.
Tiebar shown (if present) is a non-functional feature.
Dimensioning and tolerancing conform to AMSEY14.5m-1994.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
Unless otherwise specified, tolerance: Decimal ± 0.05
Dimension b applies to the metallized terminal and is measured
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Connect Exp. DAP (PAD) to AVSS with multiple vias to a low
thermal impedance plane
0.90 Max
36
25
C
37
24
48X 0.40
0. 2 REF
BOTTOM VIEW
SIDE VIEW
DETAIL "X"
4X 5.50
0. 00 MIN.
0. 05 MAX.
5
13
48
48X 0.25
1
12
0.10
44X 0.50
SEATING PLANE
M C
SEE DETAIL "X"
0.10
4
October 1, 2010
A
0.08
C
INDEX AREA
B
C
PIN 1
FN6807.4
6
C