AD7851ARZ Analog Devices Inc, AD7851ARZ Datasheet - Page 11

• Manufacturer Part Number: AD7851ARZ
• Description: IC ADC 14BIT SRL 333KSPS 24-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD7851ARZ

• Number Of Bits: 14
• Sampling Rate (per Second): 333k
• Data Interface: 8051, QSPI™, Serial, SPI™ µP
• Number Of Converters: 2
• Power Dissipation (max): 89.25mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CONTROL REGISTER
The arrangement of the control register is shown below. The control register is a write-only register and contains 14 bits of data. The
control register is selected by putting two 1s in ADDR1 and ADDR0. The function of the bits in the control register are described
below. The power-up status of all bits is 0.
Bit No.
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CALMD
0
0
0
0
1
1
1
1
REV. B
Mnemonic
ZERO
ZERO
ZERO
ZERO
PMGT1
PMGT0
RDSLT1
RDSLT0
2/3 MODE
CONVST
CALMD
CALSLT1
CALSLT0
STCAL
CALSLT1
0
0
1
1
0
0
1
1
RDSLT0
ZERO
MSB
CALSLT0
0
1
0
1
0
1
0
1
Interface Mode 1 is enabled where DIN is used as an output as well as an input. This bit is set to 0 by
default after every read cycle; thus when using Interface Mode 1, this bit needs to be set to 1 in every
write cycle.
cally reset to 0 at the end of conversion. This bit may also be used in conjunction with system calibration
(see Calibration section).
With the STCAL bit set to 0, the CALSLT1 and CALSLT0 bits are decoded to address the calibration
register for read/write of calibration coefficients (see section on Calibration Registers for more details).
Comment
These four bits must be set to 0 when writing to the control register.
Power Management Bits. These two bits are used with the SLEEP pin for putting the part into various
power-down modes (see Power-Down section for more details).
Theses two bits determine which register is addressed for the read operations. See Table II.
Interface Mode Select Bit. With this bit set to 0, Interface Mode 2 is enabled. With this bit set to 1,
Conversion Start Bit. A Logic 1 in this bit position starts a single conversion, and this bit is automati-
Calibration Mode Bit. A 0 here selects self-calibration and a 1 selects a system calibration (see Table III).
Calibration Selection Bits and Start Calibration Bit. These bits have two functions:
With the STCAL bit set to 1, the CALSLT1 and CALSLT0 bits determine the type of calibration per-
formed by the part (see Table III). The STCAL bit is automatically reset to 0 at the end of calibration.
2/3 MODE
ZERO
internal gain error, and finally the internal offset error is calibrated out. This is the default setting.
out.
lowed by the system gain error, and finally the system offset error is calibrated out.
Calibration Type
A full internal calibration is initiated where the internal DAC is calibrated followed by the
Here the internal gain error is calibrated out followed by the internal offset error calibrated
This calibrates out the internal offset error only.
This calibrates out the internal gain error only.
A full system calibration is initiated here where first the internal DAC is calibrated, fol-
Here the system gain error is calibrated out followed by the system offset error.
This calibrates out the system offset error only.
This calibrates out the system gain error only.
Control Register Bit Function Descriptions
CONVST
ZERO
Table III. Calibration Selection
CALMD
ZERO
–11–
CALSLT1
PMGT1
CALSLT0
PMGT0
RDSLT1
STCAL
LSB
AD7851