MAX11646EUA+ Maxim Integrated Products, MAX11646EUA+ Datasheet - Page 5

• Manufacturer Part Number: MAX11646EUA+
• Description: IC ADC 10BIT I2C 94.4KSPS 8UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX11646EUA+

• Number Of Bits: 10
• Sampling Rate (per Second): 94.4k
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 362mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Number Of Adc Inputs: 2
• Conversion Rate: 1 Ksps to 94.4 Ksps
• Resolution: 10 bit
• Input Type: Single-Ended
• Interface Type: I2C
• Snr: 60 dB
• Voltage Reference: Internal 4.096 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Power Dissipation: 362 mW
• Maximum Operating Temperature: + 85 C
• Input Voltage: 4.5 V to 5.5 V
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS (Figure 1) (continued)
(V
f
notation.) (Note 1)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: Measured as follows for the MAX11647:
Note 11: A master device must provide a data hold time for SDA (referred to V
Note 12: The minimum value is specified at T
Note 13: C
Note 14: f
SCL
Rise Time of SCL Signal
(Current Source Enabled)
Rise Time of SCL Signal After
Acknowledge Bit
Fall Time of SCL Signal
Rise Time of SDA Signal
Fall Time of SDA Signal
Setup Time for a STOP (P)
Condition
Capacitive Load for Each Bus
Line
Pulse Width of Spike
DD
= 1.7MHz, T
= 2.7V to 3.6V (MAX11647), V
PARAMETER
All WLP devices are 100% production tested at T
design and characterization.
For DC accuracy, the MAX11646 is tested at V
ence for both ADCs. All devices are configured for unipolar, single-ended inputs.
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Offset nulled.
Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period.
Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode.
A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant.
The absolute input voltage range for the analog inputs (AIN0/AIN1) is from GND to V
When the internal reference is configured to be available at REF (SEL[2:1] = 11), decouple REF to GND with a 0.1µF capaci-
tor and a 2kΩ series resistor (see the Typical Operating Circuit ).
ADC performance is limited by the converter’s noise floor, typically 300µV
and for the MAX11646, where N is the number of bits:
falling edge (see Figure 1).
SCL
⎡
⎢
⎢
⎣
B
⎡
⎢
⎢
⎣
⎡ ⎣
⎡ ⎣
= total capacitance of one bus line in pF.
V FS
V
must meet the minimum clock low time plus the rise/fall times.
FS
Low-Power, 1-/2-Channel, I
A
( .
( .
3 6
5 5
= T
_______________________________________________________________________________________
V
V
( .
( .
)
3 6
MIN
)
5 5
−
−
V
V FS
V
in Ultra-Tiny 1.9mm x 2.2mm Package
V
FS
to T
− −
− −
( .
2 7 . ) V
( .
4 5 . ) V
2 7
4 5
MAX
V
V
)
)
, unless otherwise noted. Typical values are at T
⎤ ⎦ ×
⎤ ⎦ ×
SYMBOL
DD
t
SU
t
t
V
t
RCL1
t
t
V REF
RCL
RDA
FDA
C
t
FCL
2
SP
REF
:
= 4.5V to 5.5V (MAX11646), V
2
STO
B
N
N
⎤
⎥
⎥
⎦
A
⎤
⎥
⎥
⎦
= +25°C.
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
Measured from 0.3V
(Notes 11 and 14)
DD
A
= 5V and the MAX11647 is tested at V
= +25°C. Specifications over temperature limits are guaranteed by
CONDITIONS
DD
DD
DD
DD
DD
to 0.7V
to 0.7V
to 0.7V
to 0.7V
to 0.7V
REF
= 2.048V (MAX11647), V
IL
DD
DD
DD
DD
DD
of SCL) to bridge the undefined region of SCL’s
(Note 12)
P-P
A
.
= +25°C. See Tables 1–5 for programming
2
C, 10-Bit ADCs
DD
MIN
.
160
20
20
20
20
20
DD
0
= 3V, with an external refer-
REF
TYP
= 4.096V (MAX11646),
MAX
160
160
160
400
80
80
10
UNITS
ns
ns
ns
ns
ns
ns
pF
ns
5