ADC084S021CIMM/NOPB National Semiconductor, ADC084S021CIMM/NOPB Datasheet - Page 15

• Manufacturer Part Number: ADC084S021CIMM/NOPB
• Description: IC ADC 8BIT 4CH 200KSPS 10-MSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC084S021CIMM/NOPB

• Number Of Bits: 8
• Sampling Rate (per Second): 200k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 5.8mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP, 10-MSOP (0.118", 3.00mm Width)
• For Use With: ADC084S021EVAL - BOARD EVALUATION FOR ADC084S021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *ADC084S021CIMM; ADC084S021CIMM; ADC084S021CIMMNOPB; ADC084S021CIMMNOPBTR; ADC084S021CIMMNOPBTR; ADC084S021CIMMTR

Applications Information
1.0 ADC084S021 OPERATION
The ADC084S021 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution dig-
ital-to-analog converter. Simplified schematics of the
ADC084S021 in both track and hold modes are shown in and
, respectively. shows the ADC084S021 in track mode: switch
SW1 connects the sampling capacitor to one of four analog
input channels through the multiplexer, and SW2 balances
the comparator inputs. The ADC084S021 is in this state for
the first three SCLK cycles after CS is brought low.
Figure 2 shows the ADC084S021 in hold mode: switch SW1
connects the sampling capacitor to ground, maintaining the
2.0 USING THE ADC084S021
An ADC084S021 timing diagram and a serial interface timing
diagram for the ADC084S021 are shown in the Timing Dia-
grams section. CS is chip select, which initiates conversions
and frames the serial data transfers. SCLK (serial clock) con-
trols both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result
is sent as a serial data stream, MSB first. Data at DIN, the
serial data input pin, is written to the ADC084S021's Control
Register. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC output data
(DOUT) is in a high impedance state when CS is high and is
active when CS is low. CS thus acts as an output enable, in
addition to being a start conversion input. Additionally, the
device goes into a power down state when CS is high and
between continuous conversion cycles.
FIGURE 1. ADC084S021 in Track Mode
FIGURE 2. ADC084S021 in Hold Mode
15
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add fixed amounts of charge to the sampling capacitor
until the comparator is balanced. When the comparator is
balanced, the digital word supplied to the DAC is the digital
representation of the analog input voltage. The ADC084S021
is in this state for the fourth through sixteenth SCLK cycles
after CS is brought low.
The time when CS is low is considered a serial frame. Each
of these frames should contain an integer multiple of 16 SCLK
cycles, during which time a conversion is performed and
clocked out at the DOUT pin and data is clocked into the DIN
pin to indicate the multiplexer address for the next conversion.
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK cy-
cles the conversion is accomplished and the data is clocked
out, MSB first, starting with the 5th clock. If there is more than
one conversion in a frame, the ADC will re-enter the track
mode on the falling edge of SCLK after the N*16th rising edge
of SCLK, and re-enter the hold/convert mode at the N*16+4th
falling edge of SCLK, where "N" is an integer.
SCLK is internally gated off when CS is high. If SCLK is
stopped in the low state while CS is high, the subsequent fall
of CS will generate a falling edge of the internal version of
SCLK, putting the ADC into the track mode. This is seen by
the ADC as the first falling edge of SCLK. If SCLK is stopped
with SCLK high, the ADC enters the track mode at the first
falling edge of SCLK after the falling edge of CS.
During each conversion, data is clocked into the device at the
DIN pin on the first 8 rising edges of SCLK after the fall of
CS. For each conversion, it is necessary to clock in the data
indicating the input that is selected for the conversion after the
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