AD7190BRUZ Analog Devices Inc, AD7190BRUZ Datasheet - Page 30

• Manufacturer Part Number: AD7190BRUZ
• Description: IC ADC 2CH 24BIT W/PGA 24TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD7190BRUZ

• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Design Resources: Precision Weigh Scale Design Using AD7190 with Internal PGA (CN0102)
• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP (0.173", 4.40mm Width)
• Resolution (bits): 24bit
• Sampling Rate: 4.8kSPS
• Input Channel Type: Pseudo Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7190
Figure 3 and Figure 4 show timing diagrams for interfacing to the
AD7190, with CS being used to decode the part.
the timing for a read operation from the output shift register of
the AD7190, and
to the input shift register. It is possible to read the same word
from the data register several times even though the DOUT/
line returns high after the first read operation. However, care
must be taken to ensure that the read operations have been com-
pleted before the next output update occurs. In continuous read
mode, the data register can be read only once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/ RDY lines are used to
communicate with the AD7190. The end of the conversion can be
monitored using the RDY bit or pin. This scheme is suitable for
interfacing to microcontrollers.
If CS is required as a decoding signal, it can be generated from a
port pin. For microcontroller interfaces, it is recommended that
SCLK idle high between data transfers.
The AD7190 can be operated with CS used as a frame synchron-
ization signal. This scheme is useful for DSP interfaces. In this
case, the first bit (MSB) is effectively clocked out by CS because
CS normally occurs after the falling edge of SCLK in DSPs. The
SCLK can continue to run between data transfers, provided the
timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s to the
DIN input. If a Logic 1 is written to the AD7190 DIN line for at
least 40 serial clock cycles, the serial interface is reset. This ensures
that the interface can be reset to a known state if the interface gets
lost due to a software error or some glitch in the system. Reset
returns the interface to the state in which it is expecting a write to
the communications register. This operation resets the contents of
all registers to their power-on values. Following a reset, the user
should allow a period of 500 μs before addressing the serial
interface.
DOUT/RDY
SCLK
DIN
CS
Figure 4
shows the timing for a write operation
0x08
0x280060
Figure 3
shows
Figure 29. Single Conversion
RDY
Rev. B | Page 30 of 40
The AD7190 can be configured to continuously convert or to
perform a single conversion. See Figure 29 through Figure 31.
Single Conversion Mode
In single conversion mode, the AD7190 is placed in power-
down mode after conversions. When a single conversion is
initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively,
in the mode register, the AD7190 powers up, performs a single
conversion, and then returns to power-down mode. The
on-chip oscillator requires 1 ms approximately to power up.
DOUT/ RDY goes low to indicate the completion of a conversion.
When the data word has been read from the data register,
DOUT/ RDY goes high. If CS is low, DOUT/ RDY remains high
until another conversion is initiated and completed. The data
register can be read several times, if required, even when
DOUT/ RDY has gone high.
If several channels are enabled, the ADC sequences through the
enabled channels and performs a conversion on each channel.
When a conversion is started, DOUT/ RDY goes high and
remains high until a valid conversion is available. As soon as the
conversion is available, DOUT/ RDY goes low. The ADC then
selects the next channel and begins a conversion. The user can
read the present conversion while the next conversion is being
performed. As soon as the next conversion is complete, the data
register is updated; therefore, the user has a limited period in
which to read the conversion. When the ADC has performed a
single conversion on each of the selected channels, it returns to
power-down mode.
If the DAT_STA bit in the mode register is set to 1, the contents
of the status register are output along with the conversion each
time that the data read is performed. The four LSBs of the status
register indicate the channel to which the conversion corresponds.
0x58
DATA